include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15
  16 /*
  17  * Environment settings
  18  */
  19
  20 /*
  21  * Serial Console Configuration
  22  */
  23
  24 /*
  25  * Bootloader Components Configuration
  26  */
  27
  28 /* I2C support */
  29 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  30 #define CONFIG_SYS_I2C_PXA
  31 #define CONFIG_PXA_STD_I2C
  32 #define CONFIG_PXA_PWR_I2C
  33 #endif
  34
  35 /* LCD support */
  36 #ifdef CONFIG_LCD
  37 #define CONFIG_PXA_LCD
  38 #define CONFIG_PXA_VGA
  39 #endif
  40
  41 /*
  42  * Networking Configuration
  43  */
  44 #ifdef  CONFIG_CMD_NET
  45
  46 #define CONFIG_DRIVER_DM9000            1
  47 #define CONFIG_DM9000_BASE              0x08000000
  48 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  49 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  50 #endif
  51
  52 /*
  53  * Clock Configuration
  54  */
  55 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  56
  57 /*
  58  * DRAM Map
  59  */
  60 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  61 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  62
  63 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  64 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  65
  66 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  67 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  68
  69 /*
  70  * NOR FLASH
  71  */
  72 #ifdef  CONFIG_CMD_FLASH
  73 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  74 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  75 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  76
  77 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  78
  79 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  80
  81 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  82 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
  83 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
  84 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
  85 #endif
  86
  87 #define CONFIG_SYS_MONITOR_LEN          0x40000
  88
  89 /* Skip factory configuration block */
  90
  91 /*
  92  * GPIO settings
  93  */
  94 #define CONFIG_SYS_GPSR0_VAL    0x00000000
  95 #define CONFIG_SYS_GPSR1_VAL    0x00020000
  96 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
  97 #define CONFIG_SYS_GPSR3_VAL    0x00000000
  98
  99 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 100 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 101 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 102 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 103
 104 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 105 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 106 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 107 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 108
 109 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 110 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 111 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 112 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 113 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 114 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 115 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 116 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 117
 118 #define CONFIG_SYS_PSSR_VAL     0x30
 119
 120 /*
 121  * Clock settings
 122  */
 123 #define CONFIG_SYS_CKEN         0x00500240
 124 #define CONFIG_SYS_CCCR         0x02000290
 125
 126 /*
 127  * Memory settings
 128  */
 129 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 130 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 131 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 132 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 133 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 134 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 135 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 136 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 137
 138 /*
 139  * PCMCIA and CF Interfaces
 140  */
 141 #define CONFIG_SYS_MECR_VAL     0x00000000
 142 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 143 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 144 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 145 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 146 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 147 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 148
 149 #include "pxa-common.h"
 150
 151 #endif /* __CONFIG_H */