include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 /* Avoid overwriting factory configuration block */
  16 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  17
  18 /*
  19  * Environment settings
  20  */
  21
  22 /*
  23  * Serial Console Configuration
  24  */
  25
  26 /*
  27  * Bootloader Components Configuration
  28  */
  29
  30 /* I2C support */
  31 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  32 #define CONFIG_SYS_I2C_PXA
  33 #define CONFIG_PXA_STD_I2C
  34 #define CONFIG_PXA_PWR_I2C
  35 #endif
  36
  37 /* LCD support */
  38 #ifdef CONFIG_LCD
  39 #define CONFIG_PXA_LCD
  40 #define CONFIG_PXA_VGA
  41 #define CONFIG_LCD_LOGO
  42 #endif
  43
  44 /*
  45  * Networking Configuration
  46  */
  47 #ifdef  CONFIG_CMD_NET
  48
  49 #define CONFIG_DRIVER_DM9000            1
  50 #define CONFIG_DM9000_BASE              0x08000000
  51 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  52 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  53 #define CONFIG_NET_RETRY_COUNT          10
  54
  55 #define CONFIG_BOOTP_BOOTFILESIZE
  56 #endif
  57
  58 /*
  59  * Clock Configuration
  60  */
  61 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  62
  63 /*
  64  * DRAM Map
  65  */
  66 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  67 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  68
  69 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  70 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  71
  72 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  73 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  74
  75 /*
  76  * NOR FLASH
  77  */
  78 #ifdef  CONFIG_CMD_FLASH
  79 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  80 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  81 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  82
  83 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  84
  85 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  86
  87 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  88 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
  89 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
  90 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
  91 #endif
  92
  93 #define CONFIG_SYS_MONITOR_BASE         0x0
  94 #define CONFIG_SYS_MONITOR_LEN          0x40000
  95
  96 /* Skip factory configuration block */
  97
  98 /*
  99  * GPIO settings
 100  */
 101 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 102 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 103 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 104 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 105
 106 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 107 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 108 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 109 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 110
 111 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 112 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 113 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 114 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 115
 116 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 117 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 118 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 119 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 120 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 121 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 122 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 123 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 124
 125 #define CONFIG_SYS_PSSR_VAL     0x30
 126
 127 /*
 128  * Clock settings
 129  */
 130 #define CONFIG_SYS_CKEN         0x00500240
 131 #define CONFIG_SYS_CCCR         0x02000290
 132
 133 /*
 134  * Memory settings
 135  */
 136 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 137 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 138 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 139 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 140 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 141 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 142 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 143 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 144
 145 /*
 146  * PCMCIA and CF Interfaces
 147  */
 148 #define CONFIG_SYS_MECR_VAL     0x00000000
 149 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 150 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 151 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 152 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 153 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 154 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 155
 156 #include "pxa-common.h"
 157
 158 #endif /* __CONFIG_H */