1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Toradex Colibri PXA270 configuration file
5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
13 * High Level Board Configuration Options
15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16 /* Avoid overwriting factory configuration block */
17 #define CONFIG_BOARD_SIZE_LIMIT 0x40000
20 * Environment settings
22 #define CONFIG_BOOTCOMMAND \
23 "if fatload mmc 0 0xa0000000 uImage; then " \
24 "bootm 0xa0000000; " \
26 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
27 "bootm 0xa0000000; " \
30 #define CONFIG_TIMESTAMP
31 #define CONFIG_CMDLINE_TAG
32 #define CONFIG_SETUP_MEMORY_TAGS
35 * Serial Console Configuration
39 * Bootloader Components Configuration
43 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
44 #define CONFIG_SYS_I2C_PXA
45 #define CONFIG_PXA_STD_I2C
46 #define CONFIG_PXA_PWR_I2C
51 #define CONFIG_PXA_LCD
52 #define CONFIG_PXA_VGA
53 #define CONFIG_LCD_LOGO
57 * Networking Configuration
61 #define CONFIG_DRIVER_DM9000 1
62 #define CONFIG_DM9000_BASE 0x08000000
63 #define DM9000_IO (CONFIG_DM9000_BASE)
64 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
65 #define CONFIG_NET_RETRY_COUNT 10
67 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
78 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
79 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
81 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
82 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
84 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
85 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
90 #ifdef CONFIG_CMD_FLASH
91 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
92 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
93 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
95 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
97 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
98 #define CONFIG_SYS_MAX_FLASH_BANKS 1
100 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
101 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
102 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
103 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
106 #define CONFIG_SYS_MONITOR_BASE 0x0
107 #define CONFIG_SYS_MONITOR_LEN 0x40000
109 /* Skip factory configuration block */
114 #define CONFIG_SYS_GPSR0_VAL 0x00000000
115 #define CONFIG_SYS_GPSR1_VAL 0x00020000
116 #define CONFIG_SYS_GPSR2_VAL 0x0002c000
117 #define CONFIG_SYS_GPSR3_VAL 0x00000000
119 #define CONFIG_SYS_GPCR0_VAL 0x00000000
120 #define CONFIG_SYS_GPCR1_VAL 0x00000000
121 #define CONFIG_SYS_GPCR2_VAL 0x00000000
122 #define CONFIG_SYS_GPCR3_VAL 0x00000000
124 #define CONFIG_SYS_GPDR0_VAL 0xc8008000
125 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
126 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
127 #define CONFIG_SYS_GPDR3_VAL 0x0061e804
129 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
130 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
131 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
132 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
133 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
134 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
135 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
136 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
138 #define CONFIG_SYS_PSSR_VAL 0x30
143 #define CONFIG_SYS_CKEN 0x00500240
144 #define CONFIG_SYS_CCCR 0x02000290
149 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
150 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
151 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
152 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
153 #define CONFIG_SYS_MDREFR_VAL 0x2003a031
154 #define CONFIG_SYS_MDMRS_VAL 0x00220022
155 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
156 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
159 * PCMCIA and CF Interfaces
161 #define CONFIG_SYS_MECR_VAL 0x00000000
162 #define CONFIG_SYS_MCMEM0_VAL 0x00028307
163 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
164 #define CONFIG_SYS_MCATT0_VAL 0x00038787
165 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
166 #define CONFIG_SYS_MCIO0_VAL 0x0002830f
167 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
169 #include "pxa-common.h"
171 #endif /* __CONFIG_H */