include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 #define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22 /*
  23  * High Level Configuration Options
  24  */
  25 #define CONFIG_OMAP     /* in a TI OMAP core */
  26 #define CONFIG_OMAP_GPIO
  27 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  28 #define CONFIG_OMAP_COMMON
  29 /* Common ARM Erratas */
  30 #define CONFIG_ARM_ERRATA_454179
  31 #define CONFIG_ARM_ERRATA_430973
  32 #define CONFIG_ARM_ERRATA_621766
  33
  34 #define CONFIG_SDRC     /* The chip has SDRC controller */
  35
  36 #include <asm/arch/cpu.h>               /* get chip and board defs */
  37 #include <asm/arch/omap.h>
  38
  39 /*
  40  * Display CPU and Board information
  41  */
  42 #define CONFIG_DISPLAY_CPUINFO
  43 #define CONFIG_DISPLAY_BOARDINFO
  44
  45 /* Clock Defines */
  46 #define V_OSCK                  26000000        /* Clock output from T2 */
  47 #define V_SCLK                  (V_OSCK >> 1)
  48
  49 #define CONFIG_MISC_INIT_R
  50
  51 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  52 #define CONFIG_SETUP_MEMORY_TAGS
  53 #define CONFIG_INITRD_TAG
  54 #define CONFIG_REVISION_TAG
  55 #define CONFIG_SERIAL_TAG
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  61                                         /* Sector */
  62 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  63
  64 /*
  65  * Hardware drivers
  66  */
  67
  68 /*
  69  * NS16550 Configuration
  70  */
  71 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  72
  73 #define CONFIG_SYS_NS16550_SERIAL
  74 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  75 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  76
  77 /*
  78  * select serial console configuration
  79  */
  80 #define CONFIG_CONS_INDEX               3
  81 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  82 #define CONFIG_SERIAL3                  3       /* UART3 */
  83
  84 /* allow to overwrite serial and ethaddr */
  85 #define CONFIG_ENV_OVERWRITE
  86 #define CONFIG_BAUDRATE                 115200
  87 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  88                                         115200}
  89
  90 #define CONFIG_GENERIC_MMC
  91 #define CONFIG_MMC
  92 #define CONFIG_OMAP_HSMMC
  93 #define CONFIG_DOS_PARTITION
  94
  95 /* USB */
  96 #define CONFIG_USB_OMAP3
  97 #define CONFIG_USB_EHCI
  98 #define CONFIG_USB_EHCI_OMAP
  99 #define CONFIG_USB_MUSB_UDC
 100 #define CONFIG_TWL4030_USB
 101
 102 /* USB device configuration */
 103 #define CONFIG_USB_DEVICE
 104 #define CONFIG_USB_TTY
 105 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 106
 107 /* commands to include */
 108 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 109 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 110 #define CONFIG_MTD_PARTITIONS
 111 #define MTDIDS_DEFAULT          "nand0=nand"
 112 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 113                                 "1920k(u-boot),256k(u-boot-env),"\
 114                                 "4m(kernel),-(fs)"
 115
 116 #define CONFIG_CMD_NAND         /* NAND support                 */
 117
 118 #define CONFIG_SYS_NO_FLASH
 119 #define CONFIG_SYS_I2C
 120 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 121 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 122 #define CONFIG_SYS_I2C_OMAP34XX
 123 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 125 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 126 #define CONFIG_I2C_MULTI_BUS
 127
 128 /*
 129  * TWL4030
 130  */
 131 #define CONFIG_TWL4030_POWER
 132 #define CONFIG_TWL4030_LED
 133
 134 /*
 135  * Board NAND Info.
 136  */
 137 #define CONFIG_NAND_OMAP_GPMC
 138 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 139                                                         /* to access nand */
 140 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 141                                                         /* to access nand at */
 142                                                         /* CS0 */
 143 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 144                                                         /* devices */
 145
 146 /* Environment information */
 147 #define CONFIG_EXTRA_ENV_SETTINGS \
 148         "loadaddr=0x82000000\0" \
 149         "usbtty=cdc_acm\0" \
 150         "console=ttyO2,115200n8\0" \
 151         "mpurate=500\0" \
 152         "vram=12M\0" \
 153         "dvimode=1024x768MR-16@60\0" \
 154         "defaultdisplay=dvi\0" \
 155         "mmcdev=0\0" \
 156         "mmcroot=/dev/mmcblk0p2 rw\0" \
 157         "mmcrootfstype=ext4 rootwait\0" \
 158         "nandroot=/dev/mtdblock4 rw\0" \
 159         "nandrootfstype=ubifs\0" \
 160         "mmcargs=setenv bootargs console=${console} " \
 161                 "mpurate=${mpurate} " \
 162                 "vram=${vram} " \
 163                 "omapfb.mode=dvi:${dvimode} " \
 164                 "omapdss.def_disp=${defaultdisplay} " \
 165                 "root=${mmcroot} " \
 166                 "rootfstype=${mmcrootfstype}\0" \
 167         "nandargs=setenv bootargs console=${console} " \
 168                 "mpurate=${mpurate} " \
 169                 "vram=${vram} " \
 170                 "omapfb.mode=dvi:${dvimode} " \
 171                 "omapdss.def_disp=${defaultdisplay} " \
 172                 "root=${nandroot} " \
 173                 "rootfstype=${nandrootfstype}\0" \
 174         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 175         "bootscript=echo Running bootscript from mmc ...; " \
 176                 "source ${loadaddr}\0" \
 177         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 178         "mmcboot=echo Booting from mmc ...; " \
 179                 "run mmcargs; " \
 180                 "bootm ${loadaddr}\0" \
 181         "nandboot=echo Booting from nand ...; " \
 182                 "run nandargs; " \
 183                 "nand read ${loadaddr} 2a0000 400000; " \
 184                 "bootm ${loadaddr}\0" \
 185
 186 #define CONFIG_BOOTCOMMAND \
 187         "mmc dev ${mmcdev}; if mmc rescan; then " \
 188                 "if run loadbootscript; then " \
 189                         "run bootscript; " \
 190                 "else " \
 191                         "if run loaduimage; then " \
 192                                 "run mmcboot; " \
 193                         "else run nandboot; " \
 194                         "fi; " \
 195                 "fi; " \
 196         "else run nandboot; fi"
 197
 198 /*
 199  * Miscellaneous configurable options
 200  */
 201 #define CONFIG_AUTO_COMPLETE
 202 #define CONFIG_CMDLINE_EDITING
 203 #define CONFIG_TIMESTAMP
 204 #define CONFIG_SYS_AUTOLOAD             "no"
 205 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 206 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 207 /* Print Buffer Size */
 208 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 209                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 210 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 211 /* Boot Argument Buffer Size */
 212 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 213
 214 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 215                                                                 /* works on */
 216 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 217                                         0x01F00000) /* 31MB */
 218
 219 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 220                                                         /* load address */
 221
 222 /*
 223  * OMAP3 has 12 GP timers, they can be driven by the system clock
 224  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 225  * This rate is divided by a local divisor.
 226  */
 227 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 228 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 229
 230 /*-----------------------------------------------------------------------
 231  * Physical Memory Map
 232  */
 233 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 234 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 235
 236 /*-----------------------------------------------------------------------
 237  * FLASH and environment organization
 238  */
 239
 240 /* **** PISMO SUPPORT *** */
 241 /* Monitor at start of flash */
 242 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 243 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 244
 245 #define CONFIG_ENV_IS_IN_NAND
 246 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 247 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 248 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 249
 250 #if defined(CONFIG_CMD_NET)
 251 #define CONFIG_SMC911X
 252 #define CONFIG_SMC911X_32_BIT
 253 #define CM_T3X_SMC911X_BASE     0x2C000000
 254 #define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 255 #define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 256 #endif /* (CONFIG_CMD_NET) */
 257
 258 /* additions for new relocation code, must be added to all boards */
 259 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 260 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 261 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 262 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 263                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 264                                          GENERATED_GBL_DATA_SIZE)
 265
 266 /* Status LED */
 267 #define CONFIG_STATUS_LED               /* Status LED enabled */
 268 #define CONFIG_BOARD_SPECIFIC_LED
 269 #define CONFIG_GPIO_LED
 270 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 271 #define GREEN_LED_DEV                   0
 272 #define STATUS_LED_BIT                  GREEN_LED_GPIO
 273 #define STATUS_LED_STATE                STATUS_LED_ON
 274 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 275 #define STATUS_LED_BOOT                 GREEN_LED_DEV
 276
 277 #define CONFIG_SPLASHIMAGE_GUARD
 278
 279 /* GPIO banks */
 280 #ifdef CONFIG_STATUS_LED
 281 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 282 #endif
 283
 284 /* Display Configuration */
 285 #define CONFIG_OMAP3_GPIO_2
 286 #define CONFIG_OMAP3_GPIO_5
 287 #define CONFIG_VIDEO_OMAP3
 288 #define LCD_BPP         LCD_COLOR16
 289
 290 #define CONFIG_LCD
 291 #define CONFIG_SPLASH_SCREEN
 292 #define CONFIG_SPLASH_SOURCE
 293 #define CONFIG_CMD_BMP
 294 #define CONFIG_BMP_16BPP
 295 #define CONFIG_SCF0403_LCD
 296
 297 #define CONFIG_OMAP3_SPI
 298
 299 /* Defines for SPL */
 300 #define CONFIG_SPL_FRAMEWORK
 301 #define CONFIG_SPL_NAND_SIMPLE
 302
 303 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 304 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 305 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 306 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 307
 308 #define CONFIG_SPL_BOARD_INIT
 309 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 310 #define CONFIG_SPL_LIBDISK_SUPPORT
 311 #define CONFIG_SPL_I2C_SUPPORT
 312 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 313 #define CONFIG_SPL_MMC_SUPPORT
 314 #define CONFIG_SPL_SERIAL_SUPPORT
 315 #define CONFIG_SPL_NAND_SUPPORT
 316 #define CONFIG_SPL_NAND_BASE
 317 #define CONFIG_SPL_NAND_DRIVERS
 318 #define CONFIG_SPL_NAND_ECC
 319 #define CONFIG_SPL_GPIO_SUPPORT
 320 #define CONFIG_SPL_POWER_SUPPORT
 321 #define CONFIG_SPL_OMAP3_ID_NAND
 322 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 323
 324 /* NAND boot config */
 325 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 326 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 327 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 328 #define CONFIG_SYS_NAND_OOBSIZE         64
 329 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 330 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 331 /*
 332  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 333  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 334  */
 335 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 336                                          10, 11, 12 }
 337 #define CONFIG_SYS_NAND_ECCSIZE         512
 338 #define CONFIG_SYS_NAND_ECCBYTES        3
 339 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 340
 341 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 342 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 343
 344 #define CONFIG_SPL_TEXT_BASE            0x40200800
 345 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 346                                          CONFIG_SPL_TEXT_BASE)
 347
 348 /*
 349  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 350  * older x-loader implementations. And move the BSS area so that it
 351  * doesn't overlap with TEXT_BASE.
 352  */
 353 #define CONFIG_SYS_TEXT_BASE            0x80008000
 354 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 355 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 356
 357 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 358 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 359
 360 /* EEPROM */
 361 #define CONFIG_CMD_EEPROM
 362 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 363 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 364 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 365 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 366 #define CONFIG_SYS_EEPROM_SIZE                  256
 367
 368 #define CONFIG_CMD_EEPROM_LAYOUT
 369 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
 370
 371 #endif /* __CONFIG_H */