include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 #define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22 /*
  23  * High Level Configuration Options
  24  */
  25 #define CONFIG_OMAP     /* in a TI OMAP core */
  26 #define CONFIG_OMAP_GPIO
  27 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  28
  29 #define CONFIG_SDRC     /* The chip has SDRC controller */
  30
  31 #include <asm/arch/cpu.h>               /* get chip and board defs */
  32 #include <asm/arch/omap.h>
  33
  34 /* Clock Defines */
  35 #define V_OSCK                  26000000        /* Clock output from T2 */
  36 #define V_SCLK                  (V_OSCK >> 1)
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  41 #define CONFIG_SETUP_MEMORY_TAGS
  42 #define CONFIG_INITRD_TAG
  43 #define CONFIG_REVISION_TAG
  44 #define CONFIG_SERIAL_TAG
  45
  46 /*
  47  * Size of malloc() pool
  48  */
  49 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  50                                         /* Sector */
  51 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  52
  53 /*
  54  * Hardware drivers
  55  */
  56
  57 /*
  58  * NS16550 Configuration
  59  */
  60 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  61
  62 #define CONFIG_SYS_NS16550_SERIAL
  63 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  64 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  65
  66 /*
  67  * select serial console configuration
  68  */
  69 #define CONFIG_CONS_INDEX               3
  70 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  71 #define CONFIG_SERIAL3                  3       /* UART3 */
  72
  73 /* allow to overwrite serial and ethaddr */
  74 #define CONFIG_ENV_OVERWRITE
  75 #define CONFIG_BAUDRATE                 115200
  76 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  77                                         115200}
  78
  79 /* USB */
  80 #define CONFIG_USB_OMAP3
  81 #define CONFIG_USB_EHCI
  82 #define CONFIG_USB_EHCI_OMAP
  83 #define CONFIG_USB_MUSB_UDC
  84 #define CONFIG_TWL4030_USB
  85
  86 /* USB device configuration */
  87 #define CONFIG_USB_DEVICE
  88 #define CONFIG_USB_TTY
  89
  90 /* commands to include */
  91 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  92 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  93 #define CONFIG_MTD_PARTITIONS
  94 #define MTDIDS_DEFAULT          "nand0=nand"
  95 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
  96                                 "1920k(u-boot),256k(u-boot-env),"\
  97                                 "4m(kernel),-(fs)"
  98
  99 #define CONFIG_CMD_NAND         /* NAND support                 */
 100
 101 #define CONFIG_SYS_I2C
 102 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 103 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 104 #define CONFIG_SYS_I2C_OMAP34XX
 105 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 106 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 107 #define CONFIG_SYS_I2C_EEPROM_BUS       0
 108 #define CONFIG_I2C_MULTI_BUS
 109
 110 /*
 111  * TWL4030
 112  */
 113 #define CONFIG_TWL4030_POWER
 114 #define CONFIG_TWL4030_LED
 115
 116 /*
 117  * Board NAND Info.
 118  */
 119 #define CONFIG_NAND_OMAP_GPMC
 120 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 121                                                         /* to access nand */
 122 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 123                                                         /* to access nand at */
 124                                                         /* CS0 */
 125 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 126                                                         /* devices */
 127
 128 /* Environment information */
 129 #define CONFIG_EXTRA_ENV_SETTINGS \
 130         "loadaddr=0x82000000\0" \
 131         "usbtty=cdc_acm\0" \
 132         "console=ttyO2,115200n8\0" \
 133         "mpurate=500\0" \
 134         "vram=12M\0" \
 135         "dvimode=1024x768MR-16@60\0" \
 136         "defaultdisplay=dvi\0" \
 137         "mmcdev=0\0" \
 138         "mmcroot=/dev/mmcblk0p2 rw\0" \
 139         "mmcrootfstype=ext4 rootwait\0" \
 140         "nandroot=/dev/mtdblock4 rw\0" \
 141         "nandrootfstype=ubifs\0" \
 142         "mmcargs=setenv bootargs console=${console} " \
 143                 "mpurate=${mpurate} " \
 144                 "vram=${vram} " \
 145                 "omapfb.mode=dvi:${dvimode} " \
 146                 "omapdss.def_disp=${defaultdisplay} " \
 147                 "root=${mmcroot} " \
 148                 "rootfstype=${mmcrootfstype}\0" \
 149         "nandargs=setenv bootargs console=${console} " \
 150                 "mpurate=${mpurate} " \
 151                 "vram=${vram} " \
 152                 "omapfb.mode=dvi:${dvimode} " \
 153                 "omapdss.def_disp=${defaultdisplay} " \
 154                 "root=${nandroot} " \
 155                 "rootfstype=${nandrootfstype}\0" \
 156         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 157         "bootscript=echo Running bootscript from mmc ...; " \
 158                 "source ${loadaddr}\0" \
 159         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 160         "mmcboot=echo Booting from mmc ...; " \
 161                 "run mmcargs; " \
 162                 "bootm ${loadaddr}\0" \
 163         "nandboot=echo Booting from nand ...; " \
 164                 "run nandargs; " \
 165                 "nand read ${loadaddr} 2a0000 400000; " \
 166                 "bootm ${loadaddr}\0" \
 167
 168 #define CONFIG_BOOTCOMMAND \
 169         "mmc dev ${mmcdev}; if mmc rescan; then " \
 170                 "if run loadbootscript; then " \
 171                         "run bootscript; " \
 172                 "else " \
 173                         "if run loaduimage; then " \
 174                                 "run mmcboot; " \
 175                         "else run nandboot; " \
 176                         "fi; " \
 177                 "fi; " \
 178         "else run nandboot; fi"
 179
 180 /*
 181  * Miscellaneous configurable options
 182  */
 183 #define CONFIG_AUTO_COMPLETE
 184 #define CONFIG_CMDLINE_EDITING
 185 #define CONFIG_TIMESTAMP
 186 #define CONFIG_SYS_AUTOLOAD             "no"
 187 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 188 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 189 /* Print Buffer Size */
 190 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 191                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 192 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 193 /* Boot Argument Buffer Size */
 194 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 195
 196 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 197                                                                 /* works on */
 198 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 199                                         0x01F00000) /* 31MB */
 200
 201 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 202                                                         /* load address */
 203
 204 /*
 205  * OMAP3 has 12 GP timers, they can be driven by the system clock
 206  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 207  * This rate is divided by a local divisor.
 208  */
 209 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 210 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 211
 212 /*-----------------------------------------------------------------------
 213  * Physical Memory Map
 214  */
 215 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 216 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 217
 218 /*-----------------------------------------------------------------------
 219  * FLASH and environment organization
 220  */
 221
 222 /* **** PISMO SUPPORT *** */
 223 /* Monitor at start of flash */
 224 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 225 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 226
 227 #define CONFIG_ENV_IS_IN_NAND
 228 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 229 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 230 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 231
 232 #if defined(CONFIG_CMD_NET)
 233 #define CONFIG_SMC911X
 234 #define CONFIG_SMC911X_32_BIT
 235 #define CM_T3X_SMC911X_BASE     0x2C000000
 236 #define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 237 #define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 238 #endif /* (CONFIG_CMD_NET) */
 239
 240 /* additions for new relocation code, must be added to all boards */
 241 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 242 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 243 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 244 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 245                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 246                                          GENERATED_GBL_DATA_SIZE)
 247
 248 /* Status LED */
 249 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 250
 251 #define CONFIG_SPLASHIMAGE_GUARD
 252
 253 /* GPIO banks */
 254 #ifdef CONFIG_LED_STATUS
 255 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 256 #endif
 257
 258 /* Display Configuration */
 259 #define CONFIG_OMAP3_GPIO_2
 260 #define CONFIG_OMAP3_GPIO_5
 261 #define CONFIG_VIDEO_OMAP3
 262 #define LCD_BPP         LCD_COLOR16
 263
 264 #define CONFIG_SPLASH_SCREEN
 265 #define CONFIG_SPLASH_SOURCE
 266 #define CONFIG_CMD_BMP
 267 #define CONFIG_BMP_16BPP
 268 #define CONFIG_SCF0403_LCD
 269
 270 #define CONFIG_OMAP3_SPI
 271
 272 /* Defines for SPL */
 273 #define CONFIG_SPL_FRAMEWORK
 274 #define CONFIG_SPL_NAND_SIMPLE
 275
 276 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 277 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 278
 279 #define CONFIG_SPL_BOARD_INIT
 280 #define CONFIG_SPL_NAND_BASE
 281 #define CONFIG_SPL_NAND_DRIVERS
 282 #define CONFIG_SPL_NAND_ECC
 283 #define CONFIG_SPL_OMAP3_ID_NAND
 284 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 285
 286 /* NAND boot config */
 287 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 288 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 289 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 290 #define CONFIG_SYS_NAND_OOBSIZE         64
 291 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 292 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 293 /*
 294  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 295  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 296  */
 297 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 298                                          10, 11, 12 }
 299 #define CONFIG_SYS_NAND_ECCSIZE         512
 300 #define CONFIG_SYS_NAND_ECCBYTES        3
 301 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 302
 303 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 304 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 305
 306 #define CONFIG_SPL_TEXT_BASE            0x40200800
 307 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 308                                          CONFIG_SPL_TEXT_BASE)
 309
 310 /*
 311  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 312  * older x-loader implementations. And move the BSS area so that it
 313  * doesn't overlap with TEXT_BASE.
 314  */
 315 #define CONFIG_SYS_TEXT_BASE            0x80008000
 316 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 317 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 318
 319 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 320 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 321
 322 /* EEPROM */
 323 #define CONFIG_CMD_EEPROM
 324 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 328 #define CONFIG_SYS_EEPROM_SIZE                  256
 329
 330 #define CONFIG_CMD_EEPROM_LAYOUT
 331 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
 332
 333 #endif /* __CONFIG_H */