3 * Congatec Conga-QEVAl board configuration file.
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8 * Leo Sartre, <lsartre@adeneo-embedded.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
16 #include "mx6_common.h"
18 #define CONFIG_MACH_TYPE 4122
21 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
22 #define CONFIG_SPL_SPI_LOAD
26 /* Size of malloc() pool */
27 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
29 #define CONFIG_MISC_INIT_R
31 #define CONFIG_MXC_UART
32 #define CONFIG_MXC_UART_BASE UART2_BASE
35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
38 #define CONFIG_SPI_FLASH
39 #define CONFIG_SPI_FLASH_STMICRO
40 #define CONFIG_SPI_FLASH_SST
41 #define CONFIG_MXC_SPI
42 #define CONFIG_SF_DEFAULT_BUS 0
43 #define CONFIG_SF_DEFAULT_SPEED 20000000
44 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
47 #define CONFIG_IMX_THERMAL
50 #define CONFIG_SYS_I2C
51 #define CONFIG_SYS_I2C_MXC
52 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
54 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
55 #define CONFIG_SYS_I2C_SPEED 100000
59 #define CONFIG_POWER_I2C
60 #define CONFIG_POWER_PFUZE100
61 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
64 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
65 #define CONFIG_USB_ETHER_ASIX
66 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
67 #define CONFIG_MXC_USB_FLAGS 0
68 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
70 #define CONFIG_USBD_HS
72 #define CONFIG_USB_FUNCTION_MASS_STORAGE
75 #define CONFIG_VIDEO_IPUV3
76 #define CONFIG_VIDEO_BMP_RLE8
77 #define CONFIG_SPLASH_SCREEN
78 #define CONFIG_SPLASH_SCREEN_ALIGN
79 #define CONFIG_BMP_16BPP
80 #define CONFIG_VIDEO_LOGO
81 #define CONFIG_VIDEO_BMP_LOGO
83 #define CONFIG_IPUV3_CLK 198000000
85 #define CONFIG_IPUV3_CLK 264000000
87 #define CONFIG_IMX_HDMI
90 #define CONFIG_DWC_AHSATA
91 #define CONFIG_SYS_SATA_MAX_DEVICE 1
92 #define CONFIG_DWC_AHSATA_PORT_ID 0
93 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
98 #define CONFIG_FEC_MXC
100 #define IMX_FEC_BASE ENET_BASE_ADDR
101 #define CONFIG_FEC_XCV_TYPE RGMII
102 #define CONFIG_ETHPRIME "FEC"
103 #define CONFIG_FEC_MXC_PHYADDR 6
104 #define CONFIG_PHY_ATHEROS
106 /* Command definition */
108 #define CONFIG_MXC_UART_BASE UART2_BASE
109 #define CONSOLE_DEV "ttymxc1"
110 #define CONFIG_MMCROOT "/dev/mmcblk0p2"
111 #define CONFIG_SYS_MMC_ENV_DEV 0
113 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
114 #define CONFIG_EXTRA_ENV_SETTINGS \
115 "script=boot.scr\0" \
117 "fdtfile=undefined\0" \
118 "fdt_addr_r=0x18000000\0" \
121 "console=" CONSOLE_DEV "\0" \
122 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \
123 "dfu_alt_info_spl=spl raw 0x400\0" \
124 "dfu_alt_info_img=u-boot raw 0x10000\0" \
125 "dfu_alt_info=spl raw 0x400\0" \
126 "bootm_size=0x10000000\0" \
127 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
129 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
130 "update_sd_firmware=" \
131 "if test ${ip_dyn} = yes; then " \
132 "setenv get_cmd dhcp; " \
134 "setenv get_cmd tftp; " \
136 "if mmc dev ${mmcdev}; then " \
137 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
138 "setexpr fw_sz ${filesize} / 0x200; " \
139 "setexpr fw_sz ${fw_sz} + 1; " \
140 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
143 "mmcargs=setenv bootargs console=${console},${baudrate} " \
144 "root=${mmcroot}\0" \
146 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
147 "bootscript=echo Running bootscript from mmc ...; " \
149 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
150 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
151 "mmcboot=echo Booting from mmc ...; " \
153 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
154 "if run loadfdt; then " \
155 "bootz ${loadaddr} - ${fdt_addr_r}; " \
157 "if test ${boot_fdt} = try; then " \
160 "echo WARN: Cannot load the DT; " \
167 "if test $board_rev = MX6Q ; then " \
168 "setenv fdtfile imx6q-qmx6.dtb; fi; " \
169 "if test $board_rev = MX6DL ; then " \
170 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \
171 "if test $fdtfile = undefined; then " \
172 "echo WARNING: Could not determine dtb to use; fi; \0" \
173 "netargs=setenv bootargs console=${console},${baudrate} " \
175 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
176 "netboot=echo Booting from net ...; " \
178 "if test ${ip_dyn} = yes; then " \
179 "setenv get_cmd dhcp; " \
181 "setenv get_cmd tftp; " \
183 "${get_cmd} ${image}; " \
184 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
185 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
186 "bootz ${loadaddr} - ${fdt_addr_r}; " \
188 "if test ${boot_fdt} = try; then " \
191 "echo WARN: Cannot load the DT; " \
197 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
199 #define CONFIG_BOOTCOMMAND \
202 "mmc dev ${mmcdev};" \
203 "if mmc rescan; then " \
204 "if run loadbootscript; then " \
207 "if run loadimage; then " \
209 "else run netboot; " \
212 "else run netboot; fi"
214 #define CONFIG_SYS_MEMTEST_START 0x10000000
215 #define CONFIG_SYS_MEMTEST_END 0x10010000
216 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
218 /* Physical Memory Map */
219 #define CONFIG_NR_DRAM_BANKS 1
220 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
222 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
223 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
224 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
226 #define CONFIG_SYS_INIT_SP_OFFSET \
227 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
228 #define CONFIG_SYS_INIT_SP_ADDR \
229 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
231 /* Environment organization */
232 #if defined (CONFIG_ENV_IS_IN_MMC)
233 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
234 #define CONFIG_SYS_MMC_ENV_DEV 0
237 #define CONFIG_ENV_SIZE (8 * 1024)
239 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
240 #define CONFIG_ENV_OFFSET (768 * 1024)
241 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
242 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
243 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
244 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
245 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
248 #endif /* __CONFIG_CGTQMX6EVAL_H */