include/configs/capricorn-common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017-2018 NXP
   4  * Copyright 2019 Siemens AG
   5  */
   6
   7 #ifndef __IMX8X_CAPRICORN_H
   8 #define __IMX8X_CAPRICORN_H
   9
  10 #include <linux/sizes.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #include "siemens-env-common.h"
  14 #include "siemens-ccp-common.h"
  15
  16 /* SPL config */
  17 #ifdef CONFIG_SPL_BUILD
  18
  19 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  20 #define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
  21 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  22 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x800
  23
  24 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  25 #define CONFIG_SPL_STACK                0x013E000
  26 #define CONFIG_SPL_BSS_START_ADDR       0x00128000
  27 #define CONFIG_SPL_BSS_MAX_SIZE         0x1000  /* 4 KB */
  28 #define CONFIG_SYS_SPL_MALLOC_START     0x00120000
  29 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x3000  /* 12 KB */
  30 #define CONFIG_MALLOC_F_ADDR            0x00120000
  31
  32 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  33 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  34
  35 #endif /* CONFIG_SPL_BUILD */
  36
  37 #define CONFIG_FACTORYSET
  38
  39 #undef CONFIG_IDENT_STRING
  40 #define CONFIG_IDENT_STRING             GENERATE_CCP_VERSION("01", "07")
  41
  42 #define CONFIG_REMAKE_ELF
  43
  44 /* ENET Config */
  45 #define CONFIG_FEC_XCV_TYPE             RMII
  46
  47 /* ENET1 connects to base board and MUX with ESAI */
  48 #define CONFIG_FEC_ENET_DEV             1
  49 #define CONFIG_FEC_MXC_PHYADDR          0x0
  50 #define CONFIG_ETHPRIME                "eth1"
  51
  52 /* I2C Configuration */
  53 #ifndef CONFIG_SPL_BUILD
  54 /* EEPROM */
  55 #define  EEPROM_I2C_BUS         0 /* I2C0 */
  56 #define  EEPROM_I2C_ADDR        0x50
  57 /* PCA9552 */
  58 #define  PCA9552_1_I2C_BUS      1 /* I2C1 */
  59 #define  PCA9552_1_I2C_ADDR     0x60
  60 #endif /* !CONFIG_SPL_BUILD */
  61
  62 /* AHAB */
  63 #ifdef CONFIG_AHAB_BOOT
  64 #define AHAB_ENV "sec_boot=yes\0"
  65 #else
  66 #define AHAB_ENV "sec_boot=no\0"
  67 #endif
  68
  69 #define MFG_ENV_SETTINGS_DEFAULT \
  70         "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  71                 "rdinit=/linuxrc " \
  72                 "clk_ignore_unused "\
  73                 "\0" \
  74         "kboot=booti\0"\
  75         "bootcmd_mfg=run mfgtool_args;" \
  76         "if iminfo ${initrd_addr}; then " \
  77         "if test ${tee} = yes; then " \
  78                 "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  79         "else " \
  80                 "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  81         "fi; " \
  82         "else " \
  83             "echo \"Run fastboot ...\"; fastboot 0; "  \
  84         "fi;\0"
  85
  86 /* Boot M4 */
  87 #define M4_BOOT_ENV \
  88         "m4_0_image=m4_0.bin\0" \
  89         "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  90                         "${loadaddr} ${m4_0_image}\0" \
  91         "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  92
  93 #define CONFIG_MFG_ENV_SETTINGS \
  94         MFG_ENV_SETTINGS_DEFAULT \
  95         "initrd_addr=0x83100000\0" \
  96         "initrd_high=0xffffffffffffffff\0" \
  97         "emmc_dev=0\0"
  98
  99 /* Initial environment variables */
 100 #define CONFIG_EXTRA_ENV_SETTINGS \
 101         CONFIG_MFG_ENV_SETTINGS \
 102         M4_BOOT_ENV \
 103         AHAB_ENV \
 104         ENV_COMMON \
 105         "script=boot.scr\0" \
 106         "image=Image\0" \
 107         "panel=NULL\0" \
 108         "console=ttyLP2\0" \
 109         "fdt_addr=0x83000000\0" \
 110         "fdt_high=0xffffffffffffffff\0" \
 111         "cntr_addr=0x88000000\0" \
 112         "cntr_file=os_cntr_signed.bin\0" \
 113         "initrd_addr=0x83800000\0" \
 114         "initrd_high=0xffffffffffffffff\0" \
 115         "netdev=eth0\0" \
 116         "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
 117         "hostname=capricorn\0" \
 118         ENV_EMMC \
 119         ENV_NET
 120
 121 #define CONFIG_BOOTCOMMAND \
 122         "if usrbutton; then " \
 123                 "run flash_self_test; " \
 124                 "reset; " \
 125         "fi;" \
 126         "run flash_self;" \
 127         "reset;"
 128
 129 /* Default location for tftp and bootm */
 130 #define CONFIG_LOADADDR                 0x80280000
 131 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 132 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 133
 134 /* On CCP board, USDHC1 is for eMMC */
 135 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* eMMC */
 136 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 137
 138 /* Size of malloc() pool */
 139 #define CONFIG_SYS_MALLOC_LEN           ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
 140
 141 #define CONFIG_SYS_SDRAM_BASE           0x80000000
 142 #define PHYS_SDRAM_1                    0x80000000
 143 #define PHYS_SDRAM_2                    0x880000000
 144 /* DDR3 board total DDR is 1 GB */
 145 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1 GB */
 146 #define PHYS_SDRAM_2_SIZE               0x00000000      /* 0 GB */
 147
 148 /* Console buffer and boot args */
 149 #define CONFIG_SYS_CBSIZE               2048
 150 #define CONFIG_SYS_MAXARGS              64
 151 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 152
 153 /* Generic Timer Definitions */
 154 #define COUNTER_FREQUENCY               8000000 /* 8MHz */
 155
 156 #define BOOTAUX_RESERVED_MEM_BASE       0x88000000
 157 #define BOOTAUX_RESERVED_MEM_SIZE       SZ_128M /* Reserve from second 128MB */
 158
 159 #endif /* __IMX8X_CAPRICORN_H */