include/configs/calimain.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011-2014 OMICRON electronics GmbH
   4  *
   5  * Based on da850evm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   8  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Board
  16  */
  17 #define CONFIG_MACH_TYPE        MACH_TYPE_CALIMAIN
  18
  19 /*
  20  * SoC Configuration
  21  */
  22 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  23 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  24 #define CONFIG_SYS_OSCIN_FREQ           calimain_get_osc_freq()
  25 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  26 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  27 #define CONFIG_ARCH_CPU_INIT
  28 #define CONFIG_HW_WATCHDOG
  29 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
  30 #define CONFIG_SYS_WDT_PERIOD_LOW \
  31         (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
  32 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
  33 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  34
  35 /*
  36  * PLL configuration
  37  */
  38
  39 #define CONFIG_SYS_DA850_PLL0_PLLM \
  40         ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
  41 #define CONFIG_SYS_DA850_PLL1_PLLM \
  42         ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
  43
  44 /*
  45  * DDR2 memory configuration
  46  */
  47 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  48                                         DV_DDR_PHY_EXT_STRBEN | \
  49                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  50
  51 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  52         (1 << DV_DDR_SDCR_DDR2EN_SHIFT) |       \
  53         (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |    \
  54         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  55         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  56         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  57         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  58         (0x3 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  59         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  60
  61 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  62 #define CONFIG_SYS_DA850_DDR2_SDBCR2    0
  63
  64 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  65         (16 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  66         (1 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  67         (1 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  68         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  69         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  70         (7 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  71         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  72         (1 << DV_DDR_SDTMR1_WTR_SHIFT))
  73
  74 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  75         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  76         (2 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  77         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  78         (18 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  79         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  80         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  81         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
  82
  83 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x000003FF
  84 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
  85
  86 /*
  87  * Flash memory timing
  88  */
  89
  90 #define CONFIG_SYS_DA850_CS2CFG (       \
  91         DAVINCI_ABCR_WSETUP(2) |        \
  92         DAVINCI_ABCR_WSTROBE(5) |       \
  93         DAVINCI_ABCR_WHOLD(3) |         \
  94         DAVINCI_ABCR_RSETUP(1) |        \
  95         DAVINCI_ABCR_RSTROBE(14) |      \
  96         DAVINCI_ABCR_RHOLD(0) |         \
  97         DAVINCI_ABCR_TA(3) |            \
  98         DAVINCI_ABCR_ASIZE_16BIT)
  99
 100 /* single 64 MB NOR flash device connected to CS2 and CS3 */
 101 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
 102
 103 /*
 104  * Memory Info
 105  */
 106 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
 107 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 108 #define PHYS_SDRAM_1_SIZE       (128 << 20) /* SDRAM size 128MB */
 109 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 110
 111 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
 112         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
 113         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
 114         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
 115         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
 116         DAVINCI_SYSCFG_SUSPSRC_I2C)
 117
 118 /* memtest start addr */
 119 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
 120
 121 /* memtest will be run on 16MB */
 122 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (16 << 20))
 123
 124 /*
 125  * Serial Driver info
 126  */
 127 #define CONFIG_SYS_NS16550_SERIAL
 128 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 129 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 130 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 131
 132 #define CONFIG_FLASH_CFI_DRIVER
 133 #define CONFIG_SYS_FLASH_CFI
 134 #define CONFIG_SYS_FLASH_PROTECTION
 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 136 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
 137 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
 138 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 139 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
 140 #define CONFIG_ENV_ADDR \
 141         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
 142 #define CONFIG_ENV_SIZE             (128 << 10)
 143 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 144 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
 145 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
 146 #define CONFIG_SYS_MAX_FLASH_SECT \
 147         ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
 148
 149 /*
 150  * Network & Ethernet Configuration
 151  */
 152 #ifdef CONFIG_DRIVER_TI_EMAC
 153 #define CONFIG_BOOTP_DNS2
 154 #define CONFIG_BOOTP_SEND_HOSTNAME
 155 #define CONFIG_NET_RETRY_COUNT  10
 156 #endif
 157
 158 /*
 159  * U-Boot general configuration
 160  */
 161 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
 162 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size  */
 163 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 164 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
 165 #define CONFIG_LOADADDR        0xc0700000
 166 #define CONFIG_MX_CYCLIC
 167
 168 /*
 169  * Linux Information
 170  */
 171 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
 172 #define CONFIG_CMDLINE_TAG
 173 #define CONFIG_REVISION_TAG
 174 #define CONFIG_SETUP_MEMORY_TAGS
 175 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
 176 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 177 #define CONFIG_RESET_TO_RETRY
 178
 179 /*
 180  * Default environment settings
 181  * gpio0 = button, gpio1 = led green, gpio2 = led red
 182  * verify = n ... disable kernel checksum verification for faster booting
 183  */
 184 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 185         "tftpdir=calimero\0"                                            \
 186         "flashkernel=tftpboot $loadaddr $tftpdir/uImage; "              \
 187                 "erase 0x60800000 +0x400000; "                          \
 188                 "cp.b $loadaddr 0x60800000 $filesize\0"                 \
 189         "flashrootfs="                                                  \
 190                 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; "            \
 191                 "erase 0x60c00000 +0x2e00000; "                         \
 192                 "cp.b $loadaddr 0x60c00000 $filesize\0"                 \
 193         "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "           \
 194                 "protect off all; "                                     \
 195                 "erase 0x60000000 +0x80000; "                           \
 196                 "cp.b $loadaddr 0x60000000 $filesize\0"                 \
 197         "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "             \
 198                 "erase 0x60080000 +0x780000; "                          \
 199                 "cp.b $loadaddr 0x60080000 $filesize\0"                 \
 200         "erase_persistent=erase 0x63a00000 +0x600000;\0"                \
 201         "bootnor=setenv bootargs console=ttyS2,115200n8 "               \
 202                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 203                 "rootwait ethaddr=$ethaddr; "                           \
 204                 "gpio c 1; gpio s 2; bootm 0x60800000\0"                \
 205         "bootrlk=gpio s 1; gpio s 2;"                                   \
 206                 "setenv bootargs console=ttyS2,115200n8 "               \
 207                 "ethaddr=$ethaddr; bootm 0x60080000\0"                  \
 208         "boottftp=setenv bootargs console=ttyS2,115200n8 "              \
 209                 "root=/dev/mtdblock3 rw rootfstype=jffs2 "              \
 210                 "rootwait ethaddr=$ethaddr; "                           \
 211                 "tftpboot $loadaddr $tftpdir/uImage;"                   \
 212                 "gpio c 1; gpio s 2; bootm $loadaddr\0"                 \
 213         "checkupdate=if test -n $update_flag; then "                    \
 214                 "echo Previous update failed - starting RLK; "          \
 215                 "run bootrlk; fi; "                                     \
 216                 "if test -n $initial_setup; then "                      \
 217                 "echo Running initial setup procedure; "                \
 218                 "sleep 1; run flashall; fi\0"                           \
 219         "product=accessory\0"                                           \
 220         "serial=XX12345\0"                                              \
 221         "checknor="                                                     \
 222                 "if gpio i 0; then run bootnor; fi;\0"                  \
 223         "checkrlk="                                                     \
 224                 "if gpio i 0; then run bootrlk; fi;\0"                  \
 225         "checkbutton="                                                  \
 226                 "run checknor; sleep 1;"                                \
 227                 "run checknor; sleep 1;"                                \
 228                 "run checknor; sleep 1;"                                \
 229                 "run checknor; sleep 1;"                                \
 230                 "run checknor;"                                         \
 231                 "gpio s 1; gpio s 2;"                                   \
 232                 "echo ---- Release button to boot RLK ----;"            \
 233                 "run checkrlk; sleep 1;"                                \
 234                 "run checkrlk; sleep 1;"                                \
 235                 "run checkrlk; sleep 1;"                                \
 236                 "run checkrlk; sleep 1;"                                \
 237                 "run checkrlk; sleep 1;"                                \
 238                 "run checkrlk;"                                         \
 239                 "echo ---- Factory reset requested ----;"               \
 240                 "gpio c 1;"                                             \
 241                 "setenv factory_reset true;"                            \
 242                 "saveenv;"                                              \
 243                 "run bootnor;\0"                                        \
 244         "flashall=run flashrlk;"                                        \
 245                 "run flashkernel;"                                      \
 246                 "run flashrootfs;"                                      \
 247                 "setenv erase_datafs true;"                             \
 248                 "setenv initial_setup;"                                 \
 249                 "saveenv;"                                              \
 250                 "run bootnor;\0"                                        \
 251         "verify=n\0"                                                    \
 252         "clearenv=protect off all;"                                     \
 253                 "erase 0x60040000 +0x40000;\0"                          \
 254         "bootlimit=3\0"                                                 \
 255         "altbootcmd=run bootrlk\0"
 256
 257 #define CONFIG_PREBOOT                  \
 258         "echo Version: $ver; "          \
 259         "echo Serial: $serial; "        \
 260         "echo MAC: $ethaddr; "          \
 261         "echo Product: $product; "      \
 262         "gpio c 1; gpio c 2;"
 263
 264 /* additions for new relocation code, must added to all boards */
 265 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 266 /* initial stack pointer in internal SRAM */
 267 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 268
 269 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
 270
 271 #ifndef __ASSEMBLY__
 272 int calimain_get_osc_freq(void);
 273 #endif
 274
 275 #include <asm/arch/hardware.h>
 276
 277 #endif /* __CONFIG_H */