include/configs/caddy2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #define CONFIG_SYS_IMMR         0xE0000000
  29
  30 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  31 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  32 #define CONFIG_SYS_MEMTEST_END          0x00100000
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  38 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  39 #define CONFIG_SPD_EEPROM
  40 #define SPD_EEPROM_ADDRESS              0x54
  41 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  42 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  43
  44 /*
  45  * 32-bit data path mode.
  46  *
  47  * Please note that using this mode for devices with the real density of 64-bit
  48  * effectively reduces the amount of available memory due to the effect of
  49  * wrapping around while translating address to row/columns, for example in the
  50  * 256MB module the upper 128MB get aliased with contents of the lower
  51  * 128MB); normally this define should be used for devices with real 32-bit
  52  * data path.
  53  */
  54 #undef CONFIG_DDR_32BIT
  55
  56 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  60                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  61 #define CONFIG_DDR_2T_TIMING
  62 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  63                                         | DDRCDR_ODT \
  64                                         | DDRCDR_Q_DRN)
  65                                         /* 0x80080001 */
  66
  67 /*
  68  * FLASH on the Local Bus
  69  */
  70 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  71 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  72 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
  73                                          BR_PS_16 |     /*  16bit */ \
  74                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
  75                                          BR_V)          /* valid */
  76
  77 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  78                                         | OR_GPCM_XAM \
  79                                         | OR_GPCM_CSNT \
  80                                         | OR_GPCM_ACS_DIV2 \
  81                                         | OR_GPCM_XACS \
  82                                         | OR_GPCM_SCY_15 \
  83                                         | OR_GPCM_TRLX_SET \
  84                                         | OR_GPCM_EHTR_SET \
  85                                         | OR_GPCM_EAD)
  86                                         /* 0xffc06ff7 */
  87
  88 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  89 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
  90                                         | BR_PS_32 \
  91                                         | BR_MS_GPCM \
  92                                         | BR_V)
  93                                         /* 0xF0001801 */
  94 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
  95                                         | OR_GPCM_SETA)
  96                                         /* 0xfffc0208 */
  97
  98 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  99 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 100
 101 #undef CONFIG_SYS_FLASH_CHECKSUM
 102 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 103 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 104
 105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 106
 107 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 108 #define CONFIG_SYS_RAMBOOT
 109 #else
 110 #undef CONFIG_SYS_RAMBOOT
 111 #endif
 112
 113 #define CONFIG_SYS_INIT_RAM_LOCK        1
 114 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 115 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 116
 117 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 118                                          GENERATED_GBL_DATA_SIZE)
 119 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 120
 121 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 122 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 123
 124 /*
 125  * Local Bus LCRR and LBCR regs
 126  *    LCRR:  no DLL bypass, Clock divider is 4
 127  * External Local Bus rate is
 128  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 129  */
 130 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 131 #define CONFIG_SYS_LBC_LBCR     0x00000000
 132
 133 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 134
 135 /*
 136  * Serial Port
 137  */
 138 #define CONFIG_SYS_NS16550_SERIAL
 139 #define CONFIG_SYS_NS16550_REG_SIZE     1
 140 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 141
 142 #define CONFIG_SYS_BAUDRATE_TABLE  \
 143                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 144
 145 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 146 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 147
 148 /* I2C */
 149 #define CONFIG_SYS_I2C
 150 #define CONFIG_SYS_I2C_FSL
 151 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 152 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 153 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 154 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 155 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 156 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 157 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 158 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 159
 160 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 161
 162 /* TSEC */
 163 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 164 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 165 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 166 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 167
 168 /*
 169  * General PCI
 170  * Addresses are mapped 1-1.
 171  */
 172 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 173 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 174 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 175 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 176 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 177 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 178 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 179 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 180 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 181
 182 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 183 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 184 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 185 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 186 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 187 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 188 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 189 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 190 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 191
 192 #if defined(CONFIG_PCI)
 193
 194 #undef CONFIG_EEPRO100
 195 #undef CONFIG_TULIP
 196
 197 #if !defined(CONFIG_PCI_PNP)
 198         #define PCI_ENET0_IOADDR        0xFIXME
 199         #define PCI_ENET0_MEMADDR       0xFIXME
 200         #define PCI_IDSEL_NUMBER        0xFIXME
 201 #endif
 202
 203 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 204 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 205
 206 #endif  /* CONFIG_PCI */
 207
 208 /*
 209  * TSEC configuration
 210  */
 211
 212 #if defined(CONFIG_TSEC_ENET)
 213
 214 #define CONFIG_GMII                     /* MII PHY management */
 215 #define CONFIG_TSEC1
 216 #define CONFIG_TSEC1_NAME       "TSEC0"
 217 #define CONFIG_TSEC2
 218 #define CONFIG_TSEC2_NAME       "TSEC1"
 219 #define CONFIG_PHY_M88E1111
 220 #define TSEC1_PHY_ADDR          0x08
 221 #define TSEC2_PHY_ADDR          0x10
 222 #define TSEC1_PHYIDX            0
 223 #define TSEC2_PHYIDX            0
 224 #define TSEC1_FLAGS             TSEC_GIGABIT
 225 #define TSEC2_FLAGS             TSEC_GIGABIT
 226
 227 /* Options are: TSEC[0-1] */
 228 #define CONFIG_ETHPRIME         "TSEC0"
 229
 230 #endif  /* CONFIG_TSEC_ENET */
 231
 232 /*
 233  * Environment
 234  */
 235 #ifndef CONFIG_SYS_RAMBOOT
 236         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 237         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 238         #define CONFIG_ENV_SIZE         0x2000
 239
 240 /* Address and size of Redundant Environment Sector     */
 241 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 242 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 243
 244 #else
 245         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 246         #define CONFIG_ENV_SIZE         0x2000
 247 #endif
 248
 249 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 250 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 251
 252 /*
 253  * BOOTP options
 254  */
 255 #define CONFIG_BOOTP_BOOTFILESIZE
 256
 257 /*
 258  * Command line configuration.
 259  */
 260 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 261 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 262 #define CONFIG_RTC_RX8025
 263
 264 /* Pass Ethernet MAC to VxWorks */
 265 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 266
 267 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 268
 269 /*
 270  * Miscellaneous configurable options
 271  */
 272 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 273
 274 /*
 275  * For booting Linux, the board info and command line data
 276  * have to be in the first 256 MB of memory, since this is
 277  * the maximum mapped by the Linux kernel during initialization.
 278  */
 279 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 280
 281 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 282
 283 /* System IO Config */
 284 #define CONFIG_SYS_SICRH 0
 285 #define CONFIG_SYS_SICRL SICRL_LDP_A
 286
 287 #define CONFIG_SYS_HID0_INIT    0x000000000
 288 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 289                                  HID0_ENABLE_INSTRUCTION_CACHE)
 290
 291 #define CONFIG_SYS_HID2         HID2_HBE
 292
 293 #define CONFIG_SYS_GPIO1_PRELIM
 294 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 295 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 296
 297 #define CONFIG_SYS_GPIO2_PRELIM
 298 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 299 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 300
 301 #ifdef CONFIG_PCI
 302 #define CONFIG_PCI_INDIRECT_BRIDGE
 303 #endif
 304
 305 #if defined(CONFIG_CMD_KGDB)
 306 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 307 #endif
 308
 309 /*
 310  * Environment Configuration
 311  */
 312 #define CONFIG_ENV_OVERWRITE
 313
 314 #if defined(CONFIG_TSEC_ENET)
 315 #define CONFIG_HAS_ETH0
 316 #define CONFIG_HAS_ETH1
 317 #endif
 318
 319 #define CONFIG_HOSTNAME         "VME8349"
 320 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 321 #define CONFIG_BOOTFILE         "uImage"
 322
 323 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 324
 325 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 326         "netdev=eth0\0"                                                 \
 327         "hostname=vme8349\0"                                            \
 328         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 329                 "nfsroot=${serverip}:${rootpath}\0"                     \
 330         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 331         "addip=setenv bootargs ${bootargs} "                            \
 332                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 333                 ":${hostname}:${netdev}:off panic=1\0"                  \
 334         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 335         "flash_nfs=run nfsargs addip addtty;"                           \
 336                 "bootm ${kernel_addr}\0"                                \
 337         "flash_self=run ramargs addip addtty;"                          \
 338                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 339         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 340                 "bootm\0"                                               \
 341         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 342         "update=protect off fff00000 fff3ffff; "                        \
 343                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 344         "upd=run load update\0"                                         \
 345         "fdtaddr=780000\0"                                              \
 346         "fdtfile=vme8349.dtb\0"                                         \
 347         ""
 348
 349 #define CONFIG_NFSBOOTCOMMAND                                           \
 350         "setenv bootargs root=/dev/nfs rw "                             \
 351                 "nfsroot=$serverip:$rootpath "                          \
 352                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 353                                                         "$netdev:off "  \
 354                 "console=$consoledev,$baudrate $othbootargs;"           \
 355         "tftp $loadaddr $bootfile;"                                     \
 356         "tftp $fdtaddr $fdtfile;"                                       \
 357         "bootm $loadaddr - $fdtaddr"
 358
 359 #define CONFIG_RAMBOOTCOMMAND                                           \
 360         "setenv bootargs root=/dev/ram rw "                             \
 361                 "console=$consoledev,$baudrate $othbootargs;"           \
 362         "tftp $ramdiskaddr $ramdiskfile;"                               \
 363         "tftp $loadaddr $bootfile;"                                     \
 364         "tftp $fdtaddr $fdtfile;"                                       \
 365         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 366
 367 #define CONFIG_BOOTCOMMAND      "run flash_self"
 368
 369 #ifndef __ASSEMBLY__
 370 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 371                      unsigned char *buffer, int len);
 372 #endif
 373
 374 #endif  /* __CONFIG_H */