1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * specific parts for B&R T-Series Motherboard
7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
11 #ifndef __CONFIG_BRPPT1_H__
12 #define __CONFIG_BRPPT1_H__
14 #include <configs/bur_cfg_common.h>
15 #include <configs/bur_am335x_common.h>
16 #include <linux/stringify.h>
17 /* ------------------------------------------------------------------------- */
19 #define CONFIG_SYS_BOOTM_LEN SZ_32M
22 #define V_OSCK 26000000 /* Clock output from T2 */
23 #define V_SCLK (V_OSCK)
26 * When we have NAND flash we expect to be making use of mtdparts,
27 * both for ease of use in U-Boot and for passing information on to
31 #ifdef CONFIG_SPL_OS_BOOT
32 /* RAW SD card / eMMC */
34 #endif /* CONFIG_SPL_OS_BOOT */
36 #ifdef CONFIG_MTD_RAW_NAND
37 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
38 #endif /* CONFIG_MTD_RAW_NAND */
40 #ifdef CONFIG_MTD_RAW_NAND
42 "cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
43 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
44 "nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
45 "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
46 "b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
47 "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
48 "b_tgts_std=usb0 nand net\0" \
49 "b_tgts_rcy=net usb0 nand\0" \
50 "b_tgts_pme=usb0 nand net\0"
53 #endif /* CONFIG_MTD_RAW_NAND */
56 "t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
57 "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
59 "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
60 "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
61 "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
62 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
63 "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
64 "t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
65 "b_mode=${b_mode}\0" \
67 "load ${loaddev}:1 ${loadaddr} zImage && " \
68 "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
69 "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
70 "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
71 "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
72 "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
73 "b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
74 "b_tgts_rcy=t30lgcy#1 usb0 net\0" \
75 "b_tgts_pme=net usb0 mmc0 mmc1\0" \
78 #ifdef CONFIG_ENV_IS_IN_MMC
81 "cfgscr=mw ${dtbaddr} 0;" \
82 " mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
83 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
86 #endif /* CONFIG_MMC */
91 "cfgscr=mw ${dtbaddr} 0;" \
92 " sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
93 " fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
96 #endif /* CONFIG_SPI */
98 #define LOAD_OFFSET(x) 0x8##x
100 #define CONFIG_EXTRA_ENV_SETTINGS \
103 "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
104 "cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
105 "dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
106 "loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
107 "ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
108 "console=ttyO0,115200n8\0" \
109 "optargs=consoleblank=0 quiet panic=2\0" \
111 "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
112 "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
116 "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
117 " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
118 " else setenv b_tgts ${b_tgts_std}; fi\0" \
119 "b_default=run b_deftgts; for target in ${b_tgts};"\
120 " do echo \"### booting ${target} ###\"; run b_${target};" \
121 " if test ${b_break} = 1; then; exit; fi; done\0"
123 #ifdef CONFIG_MTD_RAW_NAND
125 * GPMC block. We support 1 device and the physical address to
126 * access CS0 at is 0x8000000.
128 #define CONFIG_SYS_MAX_NAND_DEVICE 1
129 #define CONFIG_SYS_NAND_BASE 0x8000000
130 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
131 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
132 10, 11, 12, 13, 14, 15, 16, 17, \
133 18, 19, 20, 21, 22, 23, 24, 25, \
134 26, 27, 28, 29, 30, 31, 32, 33, \
135 34, 35, 36, 37, 38, 39, 40, 41, \
136 42, 43, 44, 45, 46, 47, 48, 49, \
137 50, 51, 52, 53, 54, 55, 56, 57, }
139 #define CONFIG_SYS_NAND_ECCSIZE 512
140 #define CONFIG_SYS_NAND_ECCBYTES 14
142 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
144 #define CONFIG_NAND_OMAP_GPMC_WSCFG 1
145 #endif /* CONFIG_MTD_RAW_NAND */
147 #if defined(CONFIG_ENV_IS_IN_NAND)
148 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
151 #endif /* ! __CONFIG_BRPPT1_H__ */