1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
11 #define CONFIG_SPL_MAX_SIZE 0x00100000
12 #define CONFIG_SPL_BSS_START_ADDR 0x04000000
13 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
16 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x00200000
18 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80010000
21 #ifdef CONFIG_SPL_MMC_SUPPORT
22 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
27 * CPU and Board Configuration Options
31 * Miscellaneous configurable options
33 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
38 #define CONFIG_SYS_PBSIZE \
39 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
42 * max number of command args
44 #define CONFIG_SYS_MAXARGS 16
47 * Boot Argument Buffer Size
49 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
52 * Size of malloc() pool
53 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
55 #define CONFIG_SYS_MALLOC_LEN (512 << 10)
57 /* DT blob (fdt) address */
58 #define CONFIG_SYS_FDT_BASE 0x800f0000
63 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
64 #define PHYS_SDRAM_1 \
65 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
66 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
67 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
68 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
71 * Serial console configuration
73 #define CONFIG_SYS_NS16550_SERIAL
74 #ifndef CONFIG_DM_SERIAL
75 #define CONFIG_SYS_NS16550_REG_SIZE -4
77 #define CONFIG_SYS_NS16550_CLK 19660800
79 /* Init Stack Pointer */
80 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
81 GENERATED_GBL_DATA_SIZE)
84 * Load address and memory test area should agree with
85 * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
87 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
90 * memtest works on 512 MB in DRAM
94 * FLASH and environment organization
97 /* use CFI framework */
99 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
100 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
103 #ifdef CONFIG_CFI_FLASH
104 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
105 #endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
106 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
107 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
108 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
109 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
111 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
114 /* max number of memory banks */
116 * There are 4 banks supported for this Controller,
117 * but we have only 1 bank connected to flash on board
119 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
120 #define CONFIG_SYS_MAX_FLASH_BANKS 1
122 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
124 /* max number of sectors on one chip */
125 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
126 #define CONFIG_SYS_MAX_FLASH_SECT 512
133 * For booting Linux, the board info and command line data
134 * have to be in the first 16 MB of memory, since this is
135 * the maximum mapped by the Linux kernel during initialization.
138 /* Initial Memory map for Linux*/
139 #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
140 /* Increase max gunzip size */
141 #define CONFIG_SYS_BOOTM_LEN (64 << 20)
143 /* When we use RAM as ENV */
145 /* Enable distro boot */
146 #define BOOT_TARGET_DEVICES(func) \
149 #include <config_distro_bootcmd.h>
151 #define CONFIG_EXTRA_ENV_SETTINGS \
152 "kernel_addr_r=0x00080000\0" \
153 "pxefile_addr_r=0x01f00000\0" \
154 "scriptaddr=0x01f00000\0" \
155 "fdt_addr_r=0x02000000\0" \
156 "ramdisk_addr_r=0x02800000\0" \
159 #endif /* __CONFIG_H */