1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9263EK board.
13 #include <linux/stringify.h>
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
19 #include <asm/hardware.h>
21 /* ARM asynchronous clock */
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
23 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
30 #define LCD_BPP LCD_COLOR8
33 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
34 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
36 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
37 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
39 /* NOR flash, if populated */
40 #ifdef CONFIG_SYS_USE_NORFLASH
41 #define PHYS_FLASH_1 0x10000000
42 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
44 #define CONFIG_SYS_MONITOR_SEC 1:0-3
45 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
47 /* Address and size of Primary Environment Sector */
49 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
52 "protect off ${monitor_base} +${filesize};" \
53 "erase ${monitor_base} +${filesize};" \
54 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
55 "protect on ${monitor_base} +${filesize}\0"
57 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
58 #define MASTER_PLL_MUL 171
59 #define MASTER_PLL_DIV 14
60 #define MASTER_PLL_OUT 3
63 #define CONFIG_SYS_MOR_VAL \
64 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
65 #define CONFIG_SYS_PLLAR_VAL \
66 (AT91_PMC_PLLAR_29 | \
67 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
68 AT91_PMC_PLLXR_PLLCOUNT(63) | \
69 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
70 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
72 /* PCK/2 = MCK Master Clock from PLLA */
73 #define CONFIG_SYS_MCKR1_VAL \
74 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
77 /* PCK/2 = MCK Master Clock from PLLA */
78 #define CONFIG_SYS_MCKR2_VAL \
79 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
82 /* define PDC[31:16] as DATA[31:16] */
83 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
84 /* no pull-up for D[31:16] */
85 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
86 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
87 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
88 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
89 AT91_MATRIX_CSA_EBI_CS1A)
92 /* SDRAMC_MR Mode register */
93 #define CONFIG_SYS_SDRC_MR_VAL1 0
94 /* SDRAMC_TR - Refresh Timer register */
95 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
96 /* SDRAMC_CR - Configuration register*/
97 #define CONFIG_SYS_SDRC_CR_VAL \
101 AT91_SDRAMC_CAS_3 | \
102 AT91_SDRAMC_DBW_32 | \
103 (1 << 8) | /* Write Recovery Delay */ \
104 (7 << 12) | /* Row Cycle Delay */ \
105 (2 << 16) | /* Row Precharge Delay */ \
106 (2 << 20) | /* Row to Column Delay */ \
107 (5 << 24) | /* Active to Precharge Delay */ \
108 (1 << 28)) /* Exit Self Refresh to Active Delay */
110 /* Memory Device Register -> SDRAM */
111 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
112 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
113 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
115 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
116 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
117 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
118 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
119 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
120 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
121 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
122 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
123 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
124 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
125 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
126 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
127 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
128 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
130 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
131 #define CONFIG_SYS_SMC0_SETUP0_VAL \
132 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
133 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
134 #define CONFIG_SYS_SMC0_PULSE0_VAL \
135 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
136 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
137 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
138 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
139 #define CONFIG_SYS_SMC0_MODE0_VAL \
140 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
141 AT91_SMC_MODE_DBW_16 | \
142 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
144 /* user reset enable */
145 #define CONFIG_SYS_RSTC_RMR_VAL \
147 AT91_RSTC_MR_URSTEN | \
148 AT91_RSTC_MR_ERSTL(15))
150 /* Disable Watchdog */
151 #define CONFIG_SYS_WDTC_WDMR_VAL \
152 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
153 AT91_WDT_MR_WDV(0xfff) | \
154 AT91_WDT_MR_WDDIS | \
155 AT91_WDT_MR_WDD(0xfff))
158 #include <linux/stringify.h>
162 #ifdef CONFIG_CMD_NAND
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
165 #define CONFIG_SYS_NAND_DBW_8 1
166 /* our ALE is AD21 */
167 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
168 /* our CLE is AD22 */
169 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
170 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
171 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
175 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */