include/configs/at91sam9263ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * Configuation settings for the AT91SAM9263EK board.
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 /*
  16  * SoC must be defined first, before hardware.h is included.
  17  * In this case SoC is defined in boards.cfg.
  18  */
  19 #include <asm/hardware.h>
  20
  21 /* ARM asynchronous clock */
  22 #define CONFIG_SYS_AT91_MAIN_CLOCK      16367660 /* 16.367 MHz crystal */
  23 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  24
  25 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  26 #else
  27 #define CONFIG_SYS_USE_NORFLASH
  28 #endif
  29
  30 /*
  31  * Hardware drivers
  32  */
  33
  34 /* LCD */
  35 #define LCD_BPP                         LCD_COLOR8
  36 #define CONFIG_LCD_LOGO                 1
  37 #undef LCD_TEST_PATTERN
  38 #define CONFIG_LCD_INFO                 1
  39 #define CONFIG_LCD_INFO_BELOW_LOGO      1
  40
  41 /* SDRAM */
  42 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS1
  43 #define CONFIG_SYS_SDRAM_SIZE           0x04000000
  44
  45 #define CONFIG_SYS_INIT_SP_ADDR \
  46         (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  47
  48 /* NOR flash, if populated */
  49 #ifdef CONFIG_SYS_USE_NORFLASH
  50 #define PHYS_FLASH_1                            0x10000000
  51 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
  52 #define CONFIG_SYS_MAX_FLASH_SECT               256
  53
  54 #define CONFIG_SYS_MONITOR_SEC  1:0-3
  55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  56 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
  57
  58 /* Address and size of Primary Environment Sector */
  59
  60 #define CONFIG_EXTRA_ENV_SETTINGS       \
  61         "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
  62         "update=" \
  63                 "protect off ${monitor_base} +${filesize};" \
  64                 "erase ${monitor_base} +${filesize};" \
  65                 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
  66                 "protect on ${monitor_base} +${filesize}\0"
  67
  68 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  69 #define MASTER_PLL_MUL          171
  70 #define MASTER_PLL_DIV          14
  71 #define MASTER_PLL_OUT          3
  72
  73 /* clocks */
  74 #define CONFIG_SYS_MOR_VAL                                              \
  75                 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
  76 #define CONFIG_SYS_PLLAR_VAL                                    \
  77         (AT91_PMC_PLLAR_29 |                                    \
  78         AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
  79         AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
  80         AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
  81         AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
  82
  83 /* PCK/2 = MCK Master Clock from PLLA */
  84 #define CONFIG_SYS_MCKR1_VAL            \
  85         (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
  86          AT91_PMC_MCKR_MDIV_2)
  87
  88 /* PCK/2 = MCK Master Clock from PLLA */
  89 #define CONFIG_SYS_MCKR2_VAL            \
  90         (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
  91         AT91_PMC_MCKR_MDIV_2)
  92
  93 /* define PDC[31:16] as DATA[31:16] */
  94 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
  95 /* no pull-up for D[31:16] */
  96 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
  97 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  98 #define CONFIG_SYS_MATRIX_EBICSA_VAL                                    \
  99         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
 100          AT91_MATRIX_CSA_EBI_CS1A)
 101
 102 /* SDRAM */
 103 /* SDRAMC_MR Mode register */
 104 #define CONFIG_SYS_SDRC_MR_VAL1         0
 105 /* SDRAMC_TR - Refresh Timer register */
 106 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
 107 /* SDRAMC_CR - Configuration register*/
 108 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
 109                 (AT91_SDRAMC_NC_9 |                                             \
 110                  AT91_SDRAMC_NR_13 |                                            \
 111                  AT91_SDRAMC_NB_4 |                                             \
 112                  AT91_SDRAMC_CAS_3 |                                            \
 113                  AT91_SDRAMC_DBW_32 |                                           \
 114                  (1 <<  8) |            /* Write Recovery Delay */              \
 115                  (7 << 12) |            /* Row Cycle Delay */                   \
 116                  (2 << 16) |            /* Row Precharge Delay */               \
 117                  (2 << 20) |            /* Row to Column Delay */               \
 118                  (5 << 24) |            /* Active to Precharge Delay */         \
 119                  (1 << 28))             /* Exit Self Refresh to Active Delay */
 120
 121 /* Memory Device Register -> SDRAM */
 122 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 123 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 124 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 125 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 126 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 127 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 128 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 129 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 130 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 131 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 132 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 133 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 134 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 135 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 136 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 137 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 138 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 139 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 140
 141 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 142 #define CONFIG_SYS_SMC0_SETUP0_VAL                              \
 143         (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 144          AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 145 #define CONFIG_SYS_SMC0_PULSE0_VAL                              \
 146         (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 147          AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 148 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 149         (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 150 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 151         (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
 152          AT91_SMC_MODE_DBW_16 |                                 \
 153          AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 154
 155 /* user reset enable */
 156 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 157                 (AT91_RSTC_KEY |                \
 158                 AT91_RSTC_MR_URSTEN |           \
 159                 AT91_RSTC_MR_ERSTL(15))
 160
 161 /* Disable Watchdog */
 162 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 163                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 164                  AT91_WDT_MR_WDV(0xfff) |                       \
 165                  AT91_WDT_MR_WDDIS |                            \
 166                  AT91_WDT_MR_WDD(0xfff))
 167
 168 #endif
 169 #include <linux/stringify.h>
 170 #endif
 171
 172 /* NAND flash */
 173 #ifdef CONFIG_CMD_NAND
 174 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 175 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
 176 #define CONFIG_SYS_NAND_DBW_8                   1
 177 /* our ALE is AD21 */
 178 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 179 /* our CLE is AD22 */
 180 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 181 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PD15
 182 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PA22
 183 #endif
 184
 185 /* USB */
 186 #define CONFIG_USB_ATMEL
 187 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 188 #define CONFIG_USB_OHCI_NEW             1
 189 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 190 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 191 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 192 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 193
 194 #ifdef CONFIG_SYS_USE_DATAFLASH
 195
 196 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 197
 198 #elif CONFIG_SYS_USE_NANDFLASH
 199
 200 /* bootstrap + u-boot + env + linux in nandflash */
 201 #endif
 202
 203 #endif