1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9263EK board.
13 #include <linux/stringify.h>
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
19 #include <asm/hardware.h>
21 /* ARM asynchronous clock */
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
23 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
25 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
27 #define CONFIG_SYS_USE_NORFLASH
35 #define LCD_BPP LCD_COLOR8
36 #define CONFIG_LCD_LOGO 1
37 #undef LCD_TEST_PATTERN
38 #define CONFIG_LCD_INFO 1
39 #define CONFIG_LCD_INFO_BELOW_LOGO 1
40 #define CONFIG_ATMEL_LCD 1
41 #define CONFIG_ATMEL_LCD_BGR555 1
44 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
45 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
47 #define CONFIG_SYS_INIT_SP_ADDR \
48 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
50 /* NOR flash, if populated */
51 #ifdef CONFIG_SYS_USE_NORFLASH
52 #define PHYS_FLASH_1 0x10000000
53 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
54 #define CONFIG_SYS_MAX_FLASH_SECT 256
56 #define CONFIG_SYS_MONITOR_SEC 1:0-3
57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
58 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
60 /* Address and size of Primary Environment Sector */
62 #define CONFIG_EXTRA_ENV_SETTINGS \
63 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
65 "protect off ${monitor_base} +${filesize};" \
66 "erase ${monitor_base} +${filesize};" \
67 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
68 "protect on ${monitor_base} +${filesize}\0"
70 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
71 #define MASTER_PLL_MUL 171
72 #define MASTER_PLL_DIV 14
73 #define MASTER_PLL_OUT 3
76 #define CONFIG_SYS_MOR_VAL \
77 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
78 #define CONFIG_SYS_PLLAR_VAL \
79 (AT91_PMC_PLLAR_29 | \
80 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
81 AT91_PMC_PLLXR_PLLCOUNT(63) | \
82 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
83 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
85 /* PCK/2 = MCK Master Clock from PLLA */
86 #define CONFIG_SYS_MCKR1_VAL \
87 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
90 /* PCK/2 = MCK Master Clock from PLLA */
91 #define CONFIG_SYS_MCKR2_VAL \
92 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
95 /* define PDC[31:16] as DATA[31:16] */
96 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
97 /* no pull-up for D[31:16] */
98 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
99 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
100 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
101 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
102 AT91_MATRIX_CSA_EBI_CS1A)
105 /* SDRAMC_MR Mode register */
106 #define CONFIG_SYS_SDRC_MR_VAL1 0
107 /* SDRAMC_TR - Refresh Timer register */
108 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
109 /* SDRAMC_CR - Configuration register*/
110 #define CONFIG_SYS_SDRC_CR_VAL \
111 (AT91_SDRAMC_NC_9 | \
112 AT91_SDRAMC_NR_13 | \
114 AT91_SDRAMC_CAS_3 | \
115 AT91_SDRAMC_DBW_32 | \
116 (1 << 8) | /* Write Recovery Delay */ \
117 (7 << 12) | /* Row Cycle Delay */ \
118 (2 << 16) | /* Row Precharge Delay */ \
119 (2 << 20) | /* Row to Column Delay */ \
120 (5 << 24) | /* Active to Precharge Delay */ \
121 (1 << 28)) /* Exit Self Refresh to Active Delay */
123 /* Memory Device Register -> SDRAM */
124 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
125 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
126 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
127 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
128 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
129 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
130 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
131 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
132 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
133 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
134 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
135 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
136 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
137 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
138 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
139 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
140 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
141 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
143 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
144 #define CONFIG_SYS_SMC0_SETUP0_VAL \
145 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
146 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
147 #define CONFIG_SYS_SMC0_PULSE0_VAL \
148 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
149 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
150 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
151 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
152 #define CONFIG_SYS_SMC0_MODE0_VAL \
153 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
154 AT91_SMC_MODE_DBW_16 | \
155 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
157 /* user reset enable */
158 #define CONFIG_SYS_RSTC_RMR_VAL \
160 AT91_RSTC_MR_URSTEN | \
161 AT91_RSTC_MR_ERSTL(15))
163 /* Disable Watchdog */
164 #define CONFIG_SYS_WDTC_WDMR_VAL \
165 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
166 AT91_WDT_MR_WDV(0xfff) | \
167 AT91_WDT_MR_WDDIS | \
168 AT91_WDT_MR_WDD(0xfff))
171 #include <linux/stringify.h>
175 #ifdef CONFIG_CMD_NAND
176 #define CONFIG_SYS_MAX_NAND_DEVICE 1
177 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
178 #define CONFIG_SYS_NAND_DBW_8 1
179 /* our ALE is AD21 */
180 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
181 /* our CLE is AD22 */
182 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
183 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
184 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
188 #define CONFIG_RESET_PHY_R 1
189 #define CONFIG_AT91_WANTS_COMMON_PHY
192 #define CONFIG_USB_ATMEL
193 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
194 #define CONFIG_USB_OHCI_NEW 1
195 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
196 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
197 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
198 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
200 #ifdef CONFIG_SYS_USE_DATAFLASH
202 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
204 #elif CONFIG_SYS_USE_NANDFLASH
206 /* bootstrap + u-boot + env + linux in nandflash */