1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Configuation settings for the AT91SAM9263EK board.
13 #include <linux/stringify.h>
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
19 #include <asm/hardware.h>
21 /* ARM asynchronous clock */
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
23 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
25 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
27 #define CONFIG_SYS_USE_NORFLASH
35 #define LCD_BPP LCD_COLOR8
38 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
39 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
41 #define CONFIG_SYS_INIT_SP_ADDR \
42 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
44 /* NOR flash, if populated */
45 #ifdef CONFIG_SYS_USE_NORFLASH
46 #define PHYS_FLASH_1 0x10000000
47 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
48 #define CONFIG_SYS_MAX_FLASH_SECT 256
50 #define CONFIG_SYS_MONITOR_SEC 1:0-3
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
52 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
54 /* Address and size of Primary Environment Sector */
56 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
59 "protect off ${monitor_base} +${filesize};" \
60 "erase ${monitor_base} +${filesize};" \
61 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
62 "protect on ${monitor_base} +${filesize}\0"
64 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
65 #define MASTER_PLL_MUL 171
66 #define MASTER_PLL_DIV 14
67 #define MASTER_PLL_OUT 3
70 #define CONFIG_SYS_MOR_VAL \
71 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
72 #define CONFIG_SYS_PLLAR_VAL \
73 (AT91_PMC_PLLAR_29 | \
74 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
75 AT91_PMC_PLLXR_PLLCOUNT(63) | \
76 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
77 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
79 /* PCK/2 = MCK Master Clock from PLLA */
80 #define CONFIG_SYS_MCKR1_VAL \
81 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
84 /* PCK/2 = MCK Master Clock from PLLA */
85 #define CONFIG_SYS_MCKR2_VAL \
86 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
89 /* define PDC[31:16] as DATA[31:16] */
90 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
91 /* no pull-up for D[31:16] */
92 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
93 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
94 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
95 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
96 AT91_MATRIX_CSA_EBI_CS1A)
99 /* SDRAMC_MR Mode register */
100 #define CONFIG_SYS_SDRC_MR_VAL1 0
101 /* SDRAMC_TR - Refresh Timer register */
102 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
103 /* SDRAMC_CR - Configuration register*/
104 #define CONFIG_SYS_SDRC_CR_VAL \
105 (AT91_SDRAMC_NC_9 | \
106 AT91_SDRAMC_NR_13 | \
108 AT91_SDRAMC_CAS_3 | \
109 AT91_SDRAMC_DBW_32 | \
110 (1 << 8) | /* Write Recovery Delay */ \
111 (7 << 12) | /* Row Cycle Delay */ \
112 (2 << 16) | /* Row Precharge Delay */ \
113 (2 << 20) | /* Row to Column Delay */ \
114 (5 << 24) | /* Active to Precharge Delay */ \
115 (1 << 28)) /* Exit Self Refresh to Active Delay */
117 /* Memory Device Register -> SDRAM */
118 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
119 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
120 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
121 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
122 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
123 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
124 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
125 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
126 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
127 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
128 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
129 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
130 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
131 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
132 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
133 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
134 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
135 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
137 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
138 #define CONFIG_SYS_SMC0_SETUP0_VAL \
139 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
140 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
141 #define CONFIG_SYS_SMC0_PULSE0_VAL \
142 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
143 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
144 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
145 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
146 #define CONFIG_SYS_SMC0_MODE0_VAL \
147 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
148 AT91_SMC_MODE_DBW_16 | \
149 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
151 /* user reset enable */
152 #define CONFIG_SYS_RSTC_RMR_VAL \
154 AT91_RSTC_MR_URSTEN | \
155 AT91_RSTC_MR_ERSTL(15))
157 /* Disable Watchdog */
158 #define CONFIG_SYS_WDTC_WDMR_VAL \
159 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
160 AT91_WDT_MR_WDV(0xfff) | \
161 AT91_WDT_MR_WDDIS | \
162 AT91_WDT_MR_WDD(0xfff))
165 #include <linux/stringify.h>
169 #ifdef CONFIG_CMD_NAND
170 #define CONFIG_SYS_MAX_NAND_DEVICE 1
171 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
172 #define CONFIG_SYS_NAND_DBW_8 1
173 /* our ALE is AD21 */
174 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
175 /* our CLE is AD22 */
176 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
177 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
178 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
182 #define CONFIG_USB_ATMEL
183 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
184 #define CONFIG_USB_OHCI_NEW 1
185 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
186 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
187 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
188 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2