include/configs/at91sam9261ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * Configuation settings for the AT91SAM9261EK board.
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* ARM asynchronous clock */
  14 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  15 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000        /* 18.432 MHz crystal */
  16
  17 #include <asm/hardware.h>
  18
  19 /*
  20  * Hardware drivers
  21  */
  22
  23 /* LCD */
  24 #define LCD_BPP                         LCD_COLOR8
  25 #define CONFIG_LCD_LOGO
  26 #undef LCD_TEST_PATTERN
  27 #define CONFIG_LCD_INFO
  28 #define CONFIG_LCD_INFO_BELOW_LOGO
  29 #define CONFIG_ATMEL_LCD
  30 #ifdef CONFIG_AT91SAM9261EK
  31 #define CONFIG_ATMEL_LCD_BGR555
  32 #endif
  33
  34 /* SDRAM */
  35 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  36 #define CONFIG_SYS_SDRAM_SIZE           0x04000000
  37 #define CONFIG_SYS_INIT_SP_ADDR \
  38         (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  39
  40 /* NAND flash */
  41 #ifdef CONFIG_CMD_NAND
  42 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  43 #define CONFIG_SYS_NAND_BASE                    0x40000000
  44 #define CONFIG_SYS_NAND_DBW_8
  45 /* our ALE is AD22 */
  46 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
  47 /* our CLE is AD21 */
  48 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
  49 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  50 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PC15
  51
  52 #endif
  53
  54 /* Ethernet */
  55 #define CONFIG_DRIVER_DM9000
  56 #define CONFIG_DM9000_BASE              0x30000000
  57 #define DM9000_IO                       CONFIG_DM9000_BASE
  58 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  59 #define CONFIG_DM9000_USE_16BIT
  60 #define CONFIG_DM9000_NO_SROM
  61 #define CONFIG_RESET_PHY_R
  62
  63 /* USB */
  64 #define CONFIG_USB_ATMEL
  65 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  66 #define CONFIG_USB_OHCI_NEW
  67 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  68 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000      /* AT91SAM9261_UHP_BASE */
  69 #ifdef CONFIG_AT91SAM9G10EK
  70 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9g10"
  71 #else
  72 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
  73 #endif
  74 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  75
  76 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
  77
  78 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
  79
  80 #elif CONFIG_SYS_USE_DATAFLASH_CS3
  81
  82 /* bootstrap + u-boot + env + linux in dataflash on CS3 */
  83
  84 #else /* CONFIG_SYS_USE_NANDFLASH */
  85
  86 /* bootstrap + u-boot + env + linux in nandflash */
  87 #endif
  88
  89 #endif