Convert CONFIG_CMD_JFFS2 to Kconfig
[platform/kernel/u-boot.git] / include / configs / aria.h
1 /*
2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * Aria board configuration file
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #define CONFIG_ARIA 1
16
17 /*
18  * Memory map for the ARIA board:
19  *
20  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
21  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
22  * 0x3010_0000-0x3011_FFFF      On Board SRAM (128 KB) - CS6
23  * 0x3020_0000-0x3021_FFFF      FPGA (128 KB) - CS2
24  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
25  * 0x8400_0000-0x82FF_FFFF      PCI I/O space (16 MB)
26  * 0xA000_0000-0xAFFF_FFFF      PCI memory space (256 MB)
27  * 0xB000_0000-0xBFFF_FFFF      PCI memory mapped I/O space (256 MB)
28  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
29  */
30
31 /*
32  * High Level Configuration Options
33  */
34 #define CONFIG_E300             1       /* E300 Family */
35 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
36
37 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
38
39 /* video */
40
41 /* CONFIG_PCI is defined at config time */
42
43 #define CONFIG_SYS_MPC512X_CLKIN        33000000        /* in Hz */
44
45 #define CONFIG_MISC_INIT_R
46
47 #define CONFIG_SYS_IMMR                 0x80000000
48 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
49
50 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END          0x00400000
52
53 /*
54  * DDR Setup - manually set all parameters as there's no SPD etc.
55  */
56 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
57 #define CONFIG_SYS_DDR_BASE             0x00000000
58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
59 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
60
61 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
62
63 /* DDR Controller Configuration
64  *
65  * SYS_CFG:
66  *      [31:31] MDDRC Soft Reset:       Diabled
67  *      [30:30] DRAM CKE pin:           Enabled
68  *      [29:29] DRAM CLK:               Enabled
69  *      [28:28] Command Mode:           Enabled (For initialization only)
70  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
71  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
72  *      [20:19] Read Test:              DON'T USE
73  *      [18:18] Self Refresh:           Enabled
74  *      [17:17] 16bit Mode:             Disabled
75  *      [16:13] Ready Delay:            2
76  *      [12:12] Half DQS Delay:         Disabled
77  *      [11:11] Quarter DQS Delay:      Disabled
78  *      [10:08] Write Delay:            2
79  *      [07:07] Early ODT:              Disabled
80  *      [06:06] On DIE Termination:     Disabled
81  *      [05:05] FIFO Overflow Clear:    DON'T USE here
82  *      [04:04] FIFO Underflow Clear:   DON'T USE here
83  *      [03:03] FIFO Overflow Pending:  DON'T USE here
84  *      [02:02] FIFO Underlfow Pending: DON'T USE here
85  *      [01:01] FIFO Overlfow Enabled:  Enabled
86  *      [00:00] FIFO Underflow Enabled: Enabled
87  * TIME_CFG0
88  *      [31:16] DRAM Refresh Time:      0 CSB clocks
89  *      [15:8]  DRAM Command Time:      0 CSB clocks
90  *      [07:00] DRAM Precharge Time:    0 CSB clocks
91  * TIME_CFG1
92  *      [31:26] DRAM tRFC:
93  *      [25:21] DRAM tWR1:
94  *      [20:17] DRAM tWRT1:
95  *      [16:11] DRAM tDRR:
96  *      [10:05] DRAM tRC:
97  *      [04:00] DRAM tRAS:
98  * TIME_CFG2
99  *      [31:28] DRAM tRCD:
100  *      [27:23] DRAM tFAW:
101  *      [22:19] DRAM tRTW1:
102  *      [18:15] DRAM tCCD:
103  *      [14:10] DRAM tRTP:
104  *      [09:05] DRAM tRP:
105  *      [04:00] DRAM tRPA
106  */
107 #define CONFIG_SYS_MDDRC_SYS_CFG     (  (1 << 31) |     /* RST_B */ \
108                                         (1 << 30) |     /* CKE */ \
109                                         (1 << 29) |     /* CLK_ON */ \
110                                         (0 << 28) |     /* CMD_MODE */ \
111                                         (4 << 25) |     /* DRAM_ROW_SELECT */ \
112                                         (3 << 21) |     /* DRAM_BANK_SELECT */ \
113                                         (0 << 18) |     /* SELF_REF_EN */ \
114                                         (0 << 17) |     /* 16BIT_MODE */ \
115                                         (2 << 13) |     /* RDLY */ \
116                                         (0 << 12) |     /* HALF_DQS_DLY */ \
117                                         (1 << 11) |     /* QUART_DQS_DLY */ \
118                                         (2 <<  8) |     /* WDLY */ \
119                                         (0 <<  7) |     /* EARLY_ODT */ \
120                                         (1 <<  6) |     /* ON_DIE_TERMINATE */ \
121                                         (0 <<  5) |     /* FIFO_OV_CLEAR */ \
122                                         (0 <<  4) |     /* FIFO_UV_CLEAR */ \
123                                         (0 <<  1) |     /* FIFO_OV_EN */ \
124                                         (0 <<  0)       /* FIFO_UV_EN */ \
125                                      )
126
127 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
128 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x55D81189
129 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34790863
130
131 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
132 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
133 #define CONFIG_SYS_MICRON_EMR        (  (1 << 24) |     /* CMD_REQ */ \
134                                         (0 << 22) |     /* DRAM_CS */ \
135                                         (0 << 21) |     /* DRAM_RAS */ \
136                                         (0 << 20) |     /* DRAM_CAS */ \
137                                         (0 << 19) |     /* DRAM_WEB */ \
138                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
139                                         (0 << 15) |     /* */ \
140                                         (0 << 12) |     /* A12->out */ \
141                                         (0 << 11) |     /* A11->RDQS */ \
142                                         (0 << 10) |     /* A10->DQS# */ \
143                                         (0 <<  7) |     /* OCD program */ \
144                                         (0 <<  6) |     /* Rtt1 */ \
145                                         (0 <<  3) |     /* posted CAS# */ \
146                                         (0 <<  2) |     /* Rtt0 */ \
147                                         (1 <<  1) |     /* ODS */ \
148                                         (0 <<  0)       /* DLL */ \
149                                      )
150 #define CONFIG_SYS_MICRON_EMR2          0x01020000
151 #define CONFIG_SYS_MICRON_EMR3          0x01030000
152 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
153 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
154 #define CONFIG_SYS_MICRON_EMR_OCD    (  (1 << 24) |     /* CMD_REQ */ \
155                                         (0 << 22) |     /* DRAM_CS */ \
156                                         (0 << 21) |     /* DRAM_RAS */ \
157                                         (0 << 20) |     /* DRAM_CAS */ \
158                                         (0 << 19) |     /* DRAM_WEB */ \
159                                         (1 << 16) |     /* DRAM_BS[2:0] */ \
160                                         (0 << 15) |     /* */ \
161                                         (0 << 12) |     /* A12->out */ \
162                                         (0 << 11) |     /* A11->RDQS */ \
163                                         (1 << 10) |     /* A10->DQS# */ \
164                                         (7 <<  7) |     /* OCD program */ \
165                                         (0 <<  6) |     /* Rtt1 */ \
166                                         (0 <<  3) |     /* posted CAS# */ \
167                                         (1 <<  2) |     /* Rtt0 */ \
168                                         (0 <<  1) |     /* ODS (Output Drive Strength) */ \
169                                         (0 <<  0)       /* DLL */ \
170                                      )
171
172 /*
173  * Backward compatible definitions,
174  * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
175  */
176 #define CONFIG_SYS_DDRCMD_EM2           (CONFIG_SYS_MICRON_EMR2)
177 #define CONFIG_SYS_DDRCMD_EM3           (CONFIG_SYS_MICRON_EMR3)
178 #define CONFIG_SYS_DDRCMD_EN_DLL        (CONFIG_SYS_MICRON_EMR)
179 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   (CONFIG_SYS_MICRON_EMR_OCD)
180
181 /* DDR Priority Manager Configuration */
182 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
183 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
184 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
185 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
186 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
187 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
188 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
189 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
190 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
191 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
192 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
193 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
194 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
195 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
196 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
197 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
198 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
199 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
200 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
201 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
202 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
203 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
204 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
205
206 /*
207  * NOR FLASH on the Local Bus
208  */
209 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
210 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
211 #define CONFIG_SYS_FLASH_BASE           0xF8000000      /* start of FLASH */
212 #define CONFIG_SYS_FLASH_SIZE           0x08000000      /* max flash size */
213
214 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
215 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
216 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
217 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* max sectors */
218
219 #undef CONFIG_SYS_FLASH_CHECKSUM
220
221 /*
222  * NAND FLASH support
223  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
224  */
225 #define CONFIG_CMD_NAND                                 /* enable NAND support */
226 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
227 #define CONFIG_NAND_MPC5121_NFC
228 #define CONFIG_SYS_NAND_BASE            0x40000000
229 #define CONFIG_SYS_MAX_NAND_DEVICE      1
230
231 /*
232  * Configuration parameters for MPC5121 NAND driver
233  */
234 #define CONFIG_FSL_NFC_WIDTH            1
235 #define CONFIG_FSL_NFC_WRITE_SIZE       2048
236 #define CONFIG_FSL_NFC_SPARE_SIZE       64
237 #define CONFIG_FSL_NFC_CHIPS            CONFIG_SYS_MAX_NAND_DEVICE
238
239 #define CONFIG_SYS_SRAM_BASE            0x30000000
240 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
241
242 /* Make two SRAM regions contiguous */
243 #define CONFIG_SYS_ARIA_SRAM_BASE       (CONFIG_SYS_SRAM_BASE + \
244                                          CONFIG_SYS_SRAM_SIZE)
245 #define CONFIG_SYS_ARIA_SRAM_SIZE       0x00100000      /* reserve 1MB-window */
246 #define CONFIG_SYS_CS6_START            CONFIG_SYS_ARIA_SRAM_BASE
247 #define CONFIG_SYS_CS6_SIZE             CONFIG_SYS_ARIA_SRAM_SIZE
248
249 #define CONFIG_SYS_ARIA_FPGA_BASE       (CONFIG_SYS_ARIA_SRAM_BASE + \
250                                          CONFIG_SYS_ARIA_SRAM_SIZE)
251 #define CONFIG_SYS_ARIA_FPGA_SIZE       0x20000         /* 128 KB */
252
253 #define CONFIG_SYS_CS2_START            CONFIG_SYS_ARIA_FPGA_BASE
254 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_ARIA_FPGA_SIZE
255
256 #define CONFIG_SYS_CS0_CFG              0x05059150
257 #define CONFIG_SYS_CS2_CFG              (       (5 << 24) | \
258                                                 (5 << 16) | \
259                                                 (1 << 15) | \
260                                                 (0 << 14) | \
261                                                 (0 << 13) | \
262                                                 (1 << 12) | \
263                                                 (0 << 10) | \
264                                                 (3 <<  8) | /* 32 bit */ \
265                                                 (0 <<  7) | \
266                                                 (1 <<  6) | \
267                                                 (1 <<  4) | \
268                                                 (0 <<  3) | \
269                                                 (0 <<  2) | \
270                                                 (0 <<  1) | \
271                                                 (0 <<  0)   \
272                                         )
273 #define CONFIG_SYS_CS6_CFG              0x05059150
274
275 /* Use alternative CS timing for CS0 and CS2 */
276 #define CONFIG_SYS_CS_ALETIMING 0x00000005
277
278 /* Use SRAM for initial stack */
279 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
280 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_SRAM_SIZE
281
282 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
283                                          GENERATED_GBL_DATA_SIZE)
284 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
285
286 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
287 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
288
289 #ifdef  CONFIG_FSL_DIU_FB
290 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
291 #else
292 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
293 #endif
294
295 /* FPGA */
296 #define CONFIG_ARIA_FPGA                1
297
298 /*
299  * Serial Port
300  */
301 #define CONFIG_CONS_INDEX               1
302
303 /*
304  * Serial console configuration
305  */
306 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
307 #define CONFIG_SYS_PSC3
308 #if CONFIG_PSC_CONSOLE != 3
309 #error CONFIG_PSC_CONSOLE must be 3
310 #endif
311
312 #define CONFIG_SYS_BAUDRATE_TABLE  \
313         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
314
315 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
316 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
317 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
318 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
319
320 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
321
322 /*
323  * PCI
324  */
325 #ifdef CONFIG_PCI
326 #define CONFIG_PCI_INDIRECT_BRIDGE
327
328 #define CONFIG_SYS_PCI_MEM_BASE         0xA0000000
329 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
330 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000      /* 256M */
331 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + \
332                                          CONFIG_SYS_PCI_MEM_SIZE)
333 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
334 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
335 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
336 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
337 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
338
339 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
340
341 #endif
342
343 /*
344  * IIM - IC Identification Module
345  */
346 #undef CONFIG_FSL_IIM
347
348 /*
349  * Ethernet configuration
350  */
351 #define CONFIG_MPC512x_FEC              1
352 #define CONFIG_PHY_ADDR                 0x17
353 #define CONFIG_MII                      1       /* MII PHY management */
354 #define CONFIG_FEC_AN_TIMEOUT           1
355 #define CONFIG_HAS_ETH0
356
357 /*
358  * Environment
359  */
360 #define CONFIG_ENV_IS_IN_FLASH  1
361 /* This has to be a multiple of the flash sector size */
362 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + \
363                                          CONFIG_SYS_MONITOR_LEN)
364 #define CONFIG_ENV_SIZE                 0x2000
365 #define CONFIG_ENV_SECT_SIZE            0x20000 /* one sector (256K) */
366
367 /* Address and size of Redundant Environment Sector     */
368 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
369                                          CONFIG_ENV_SECT_SIZE)
370 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
371
372 #define CONFIG_LOADS_ECHO               1
373 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
374
375 #define CONFIG_CMD_REGINFO
376
377 #if defined(CONFIG_PCI)
378 #define CONFIG_CMD_PCI
379 #endif
380
381 /*
382  * Dynamic MTD partition support
383  */
384 #define CONFIG_CMD_MTDPARTS
385 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
386 #define CONFIG_FLASH_CFI_MTD
387 #define MTDIDS_DEFAULT          "nor0=f8000000.flash,nand0=mpc5121.nand"
388
389 /*
390  * NOR flash layout:
391  *
392  * F8000000 - FEAFFFFF  107 MiB         User Data
393  * FEB00000 - FFAFFFFF   16 MiB         Root File System
394  * FFB00000 - FFFEFFFF    4 MiB         Linux Kernel
395  * FFF00000 - FFFBFFFF  768 KiB         U-Boot (up to 512 KiB) and 2 x * env
396  * FFFC0000 - FFFFFFFF  256 KiB         Device Tree
397  *
398  * NAND flash layout: one big partition
399  */
400 #define MTDPARTS_DEFAULT        "mtdparts=f8000000.flash:107m(user),"   \
401                                                 "16m(rootfs),"          \
402                                                 "4m(kernel),"           \
403                                                 "768k(u-boot),"         \
404                                                 "256k(dtb);"            \
405                                         "mpc5121.nand:-(data)"
406
407 /*
408  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
409  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
410  * is set to 0xFFFF, watchdog timeouts after about 64s. For details
411  * refer to chapter 36 of the MPC5121e Reference Manual.
412  */
413 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
414 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
415
416  /*
417  * Miscellaneous configurable options
418  */
419 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
420 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
421
422 #ifdef CONFIG_CMD_KGDB
423 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
424 #else
425 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
426 #endif
427
428 /* Print Buffer Size */
429 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
430                                  sizeof(CONFIG_SYS_PROMPT) + 16)
431 /* max number of command args */
432 #define CONFIG_SYS_MAXARGS      32
433 /* Boot Argument Buffer Size */
434 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
435
436 /*
437  * For booting Linux, the board info and command line data
438  * have to be in the first 256 MB of memory, since this is
439  * the maximum mapped by the Linux kernel during initialization.
440  */
441 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
442
443 /* Cache Configuration */
444 #define CONFIG_SYS_DCACHE_SIZE          32768
445 #define CONFIG_SYS_CACHELINE_SIZE       32
446 #ifdef CONFIG_CMD_KGDB
447 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
448 #endif
449
450 #define CONFIG_SYS_HID0_INIT            0x000000000
451 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
452                                          HID0_ICE)
453 #define CONFIG_SYS_HID2 HID2_HBE
454
455 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
456
457 #ifdef CONFIG_CMD_KGDB
458 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
459 #endif
460
461 /*
462  * Environment Configuration
463  */
464 #define CONFIG_ENV_OVERWRITE
465 #define CONFIG_TIMESTAMP
466
467 #define CONFIG_HOSTNAME                 aria
468 #define CONFIG_BOOTFILE                 "aria/uImage"
469 #define CONFIG_ROOTPATH                 "/opt/eldk/ppc_6xx"
470
471 #define CONFIG_LOADADDR                 400000  /* default load addr */
472
473 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
474
475 #define CONFIG_PREBOOT  "echo;" \
476         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
477         "echo"
478
479 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
480         "u-boot_addr_r=200000\0"                                        \
481         "kernel_addr_r=600000\0"                                        \
482         "fdt_addr_r=880000\0"                                           \
483         "ramdisk_addr_r=900000\0"                                       \
484         "u-boot_addr=FFF00000\0"                                        \
485         "kernel_addr=FFB00000\0"                                        \
486         "fdt_addr=FFFC0000\0"                                           \
487         "ramdisk_addr=FEB00000\0"                                       \
488         "ramdiskfile=aria/uRamdisk\0"                           \
489         "u-boot=aria/u-boot.bin\0"                                      \
490         "fdtfile=aria/aria.dtb\0"                                       \
491         "netdev=eth0\0"                                                 \
492         "consdev=ttyPSC0\0"                                             \
493         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
494                 "nfsroot=${serverip}:${rootpath}\0"                     \
495         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
496         "addip=setenv bootargs ${bootargs} "                            \
497                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
498                 ":${hostname}:${netdev}:off panic=1\0"                  \
499         "addtty=setenv bootargs ${bootargs} "                           \
500                 "console=${consdev},${baudrate}\0"                      \
501         "flash_nfs=run nfsargs addip addtty;"                           \
502                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
503         "flash_self=run ramargs addip addtty;"                          \
504                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
505         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
506                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
507                 "run nfsargs addip addtty;"                             \
508                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
509         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
510                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
511                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
512                 "run ramargs addip addtty;"                             \
513                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
514         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
515         "update=protect off ${u-boot_addr} +${filesize};"               \
516                 "era ${u-boot_addr} +${filesize};"                      \
517                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
518         "upd=run load update\0"                                         \
519         ""
520
521 #define CONFIG_BOOTCOMMAND      "run flash_self"
522
523 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
524
525 #define OF_CPU                  "PowerPC,5121@0"
526 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
527 #define OF_TBCLK                (bd->bi_busfreq / 4)
528 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
529
530 /*-----------------------------------------------------------------------
531  * IDE/ATA stuff
532  *-----------------------------------------------------------------------
533  */
534
535 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
536 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
537 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
538
539 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
540 #define CONFIG_IDE_PREINIT
541
542 #define CONFIG_SYS_IDE_MAXBUS           1       /* 1 IDE bus            */
543 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* 1 drive per IDE bus  */
544
545 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
546 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
547
548 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
549 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
550
551 /* Offset for normal register accesses  */
552 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
553
554 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
555 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
556
557 /* Interval between registers   */
558 #define CONFIG_SYS_ATA_STRIDE           4
559
560 #define ATA_BASE_ADDR                   get_pata_base()
561
562 /*
563  * Control register bit definitions
564  */
565 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
566 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
567 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
568 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
569 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
570 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
571 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
572 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
573
574 /* Clocks in use */
575 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
576                          CLOCK_SCCR1_LPC_EN |                           \
577                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
578                          CLOCK_SCCR1_PSCFIFO_EN |                       \
579                          CLOCK_SCCR1_DDR_EN |                           \
580                          CLOCK_SCCR1_FEC_EN |                           \
581                          CLOCK_SCCR1_NFC_EN |                           \
582                          CLOCK_SCCR1_PATA_EN |                          \
583                          CLOCK_SCCR1_PCI_EN |                           \
584                          CLOCK_SCCR1_TPR_EN)
585
586 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
587                          CLOCK_SCCR2_SPDIF_EN |         \
588                          CLOCK_SCCR2_DIU_EN |           \
589                          CLOCK_SCCR2_I2C_EN)
590
591 #endif  /* __CONFIG_H */