include/configs/apf27.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  *
   4  * Configuration settings for the Armadeus Project motherboard APF27
   5  *
   6  * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_ENV_VERSION      10
  13 #define CONFIG_BOARD_NAME apf27
  14
  15 /*
  16  * SoC configurations
  17  */
  18 #define CONFIG_MX27                     /* This is a Freescale i.MX27 Chip */
  19 #define CONFIG_MACH_TYPE        1698    /* APF27 */
  20
  21 /*
  22  * Enable the call to miscellaneous platform dependent initialization.
  23  */
  24
  25 /*
  26  * SPL
  27  */
  28 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  29 #define CONFIG_SPL_MAX_SIZE     2048
  30
  31 /* NAND boot config */
  32 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x800
  34 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  35 #define CONFIG_SYS_NAND_U_BOOT_SIZE     CONFIG_SYS_MONITOR_LEN - 0x800
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41 #define CONFIG_BOOTP_DNS2
  42
  43 #define CONFIG_HOSTNAME "apf27"
  44 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
  45
  46 /*
  47  * Memory configurations
  48  */
  49 #define CONFIG_NR_DRAM_POPULATED 1
  50
  51 #define ACFG_SDRAM_MBYTE_SYZE 64
  52
  53 #define PHYS_SDRAM_1                    0xA0000000
  54 #define PHYS_SDRAM_2                    0xB0000000
  55 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  56 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (512<<10))
  57 #define CONFIG_SYS_MEMTEST_START        0xA0000000      /* memtest test area  */
  58 #define CONFIG_SYS_MEMTEST_END          0xA0300000      /* 3 MiB RAM test */
  59
  60 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE  \
  61                 + PHYS_SDRAM_1_SIZE - 0x0100000)
  62
  63 /*
  64  * FLASH organization
  65  */
  66 #define ACFG_MONITOR_OFFSET             0x00000000
  67 #define CONFIG_SYS_MONITOR_LEN          0x00100000      /* 1MiB */
  68 #define CONFIG_ENV_OVERWRITE
  69 #define CONFIG_ENV_OFFSET               0x00100000      /* NAND offset */
  70 #define CONFIG_ENV_SIZE                 0x00020000      /* 128kB  */
  71 #define CONFIG_ENV_RANGE                0X00080000      /* 512kB */
  72 #define CONFIG_ENV_OFFSET_REDUND        \
  73                 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)  /* +512kB */
  74 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE /* 512kB */
  75 #define CONFIG_FIRMWARE_OFFSET          0x00200000
  76 #define CONFIG_FIRMWARE_SIZE            0x00080000      /* 512kB  */
  77 #define CONFIG_KERNEL_OFFSET            0x00300000
  78 #define CONFIG_ROOTFS_OFFSET            0x00800000
  79
  80 /*
  81  * U-Boot general configurations
  82  */
  83 #define CONFIG_SYS_CBSIZE               2048            /* console I/O buffer */
  84 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  85                                                 /* Boot argument buffer size */
  86
  87 /*
  88  * Boot Linux
  89  */
  90 #define CONFIG_CMDLINE_TAG              /* send commandline to Kernel   */
  91 #define CONFIG_SETUP_MEMORY_TAGS        /* send memory definition to kernel */
  92 #define CONFIG_INITRD_TAG               /* send initrd params   */
  93
  94 #define CONFIG_BOOTFILE         __stringify(CONFIG_BOARD_NAME) "-linux.bin"
  95
  96 #define ACFG_CONSOLE_DEV        ttySMX0
  97 #define CONFIG_BOOTCOMMAND      "run ubifsboot"
  98 #define CONFIG_SYS_AUTOLOAD     "no"
  99 /*
 100  * Default load address for user programs and kernel
 101  */
 102 #define CONFIG_LOADADDR                 0xA0000000
 103 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 104
 105 /*
 106  * Extra Environments
 107  */
 108 #define CONFIG_EXTRA_ENV_SETTINGS \
 109         "env_version="          __stringify(CONFIG_ENV_VERSION)         "\0" \
 110         "consoledev="           __stringify(ACFG_CONSOLE_DEV)           "\0" \
 111         "mtdparts="             CONFIG_MTDPARTS_DEFAULT "\0" \
 112         "partition=nand0,6\0"                                           \
 113         "u-boot_addr="          __stringify(ACFG_MONITOR_OFFSET)        "\0" \
 114         "env_addr="             __stringify(CONFIG_ENV_OFFSET)          "\0" \
 115         "firmware_addr="        __stringify(CONFIG_FIRMWARE_OFFSET)     "\0" \
 116         "firmware_size="        __stringify(CONFIG_FIRMWARE_SIZE)       "\0" \
 117         "kernel_addr="          __stringify(CONFIG_KERNEL_OFFSET)       "\0" \
 118         "rootfs_addr="          __stringify(CONFIG_ROOTFS_OFFSET)       "\0" \
 119         "board_name="           __stringify(CONFIG_BOARD_NAME)          "\0" \
 120         "kernel_addr_r=A0000000\0" \
 121         "check_env=if test -n ${flash_env_version}; "                   \
 122                 "then env default env_version; "                        \
 123                 "else env set flash_env_version ${env_version}; env save; "\
 124                 "fi; "                                                  \
 125                 "if itest ${flash_env_version} < ${env_version}; then " \
 126                         "echo \"*** Warning - Environment version"      \
 127                         " change suggests: run flash_reset_env; reset\"; "\
 128                         "env default flash_reset_env; "\
 129                 "fi; \0"                                                \
 130         "check_flash=nand lock; nand unlock ${env_addr}; \0"    \
 131         "flash_reset_env=env default -f -a; saveenv; run update_env;"   \
 132                 "echo Flash environment variables erased!\0"            \
 133         "download_uboot=tftpboot ${loadaddr} ${board_name}"             \
 134                 "-u-boot-with-spl.bin\0"                                \
 135         "flash_uboot=nand unlock ${u-boot_addr} ;"                      \
 136                 "nand erase.part u-boot;"               \
 137                 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
 138                         "then nand lock; nand unlock ${env_addr};"      \
 139                                 "echo Flashing of uboot succeed;"       \
 140                         "else echo Flashing of uboot failed;"           \
 141                 "fi; \0"                                                \
 142         "update_uboot=run download_uboot flash_uboot\0"                 \
 143         "download_env=tftpboot ${loadaddr} ${board_name}"               \
 144                 "-u-boot-env.txt\0"                             \
 145         "flash_env=env import -t ${loadaddr}; env save; \0"             \
 146         "update_env=run download_env flash_env\0"                       \
 147         "update_all=run update_env update_uboot\0"                      \
 148         "unlock_regs=mw 10000008 0; mw 10020008 0\0"                    \
 149
 150 /*
 151  * Serial Driver
 152  */
 153 #define CONFIG_MXC_UART
 154 #define CONFIG_MXC_UART_BASE            UART1_BASE
 155
 156 /*
 157  * NOR
 158  */
 159
 160 /*
 161  * NAND
 162  */
 163
 164 #define CONFIG_MXC_NAND_REGS_BASE       0xD8000000
 165 #define CONFIG_SYS_NAND_BASE            CONFIG_MXC_NAND_REGS_BASE
 166 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 167
 168 #define CONFIG_MXC_NAND_HWECC
 169 #define CONFIG_SYS_NAND_LARGEPAGE
 170 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 171 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 172 #define CONFIG_SYS_NAND_PAGE_COUNT      CONFIG_SYS_NAND_BLOCK_SIZE / \
 173                                                 CONFIG_SYS_NAND_PAGE_SIZE
 174 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
 175 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   11
 176 #define NAND_MAX_CHIPS                  1
 177
 178 #define CONFIG_FLASH_SHOW_PROGRESS      45
 179 #define CONFIG_SYS_NAND_QUIET           1
 180
 181 /*
 182  * Partitions & Filsystems
 183  */
 184
 185 /*
 186  * Ethernet (on SOC imx FEC)
 187  */
 188 #define CONFIG_FEC_MXC
 189 #define CONFIG_FEC_MXC_PHYADDR          0x1f
 190
 191 /*
 192  * FPGA
 193  */
 194 #define CONFIG_FPGA_COUNT               1
 195 #define CONFIG_SYS_FPGA_WAIT            250 /* 250 ms */
 196 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 197 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 198 #define CONFIG_SYS_FPGA_CHECK_ERROR
 199
 200 /*
 201  * Fuses - IIM
 202  */
 203 #ifdef CONFIG_CMD_IMX_FUSE
 204 #define IIM_MAC_BANK            0
 205 #define IIM_MAC_ROW             5
 206 #define IIM0_SCC_KEY            11
 207 #define IIM1_SUID               1
 208 #endif
 209
 210 /*
 211  * I2C
 212  */
 213
 214 #ifdef CONFIG_CMD_I2C
 215 #define CONFIG_SYS_I2C
 216 #define CONFIG_SYS_I2C_MXC
 217 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 218 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 219 #define CONFIG_SYS_MXC_I2C1_SPEED       100000  /* 100 kHz */
 220 #define CONFIG_SYS_MXC_I2C1_SLAVE       0x7F
 221 #define CONFIG_SYS_MXC_I2C2_SPEED       100000  /* 100 kHz */
 222 #define CONFIG_SYS_MXC_I2C2_SLAVE       0x7F
 223 #define CONFIG_SYS_I2C_NOPROBES         { }
 224
 225 #ifdef CONFIG_CMD_EEPROM
 226 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM 24LC02 */
 227 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1       /* bytes of address */
 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* msec */
 230 #endif /* CONFIG_CMD_EEPROM */
 231 #endif /* CONFIG_CMD_I2C */
 232
 233 /*
 234  * SD/MMC
 235  */
 236 #ifdef CONFIG_CMD_MMC
 237 #define CONFIG_MXC_MCI_REGS_BASE        0x10014000
 238 #endif
 239
 240 /*
 241  * RTC
 242  */
 243 #ifdef CONFIG_CMD_DATE
 244 #define CONFIG_RTC_DS1374
 245 #define CONFIG_SYS_RTC_BUS_NUM          0
 246 #endif /* CONFIG_CMD_DATE */
 247
 248 /*
 249  * PLL
 250  *
 251  *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
 252  *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
 253  */
 254 #define CONFIG_MX27_CLK32               32768   /* 32768 or 32000 Hz crystal */
 255
 256 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
 257 /* micron 64MB */
 258 #define PHYS_SDRAM_1_SIZE                       0x04000000 /* 64 MB */
 259 #define PHYS_SDRAM_2_SIZE                       0x04000000 /* 64 MB */
 260 #endif
 261
 262 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
 263 /* micron 128MB */
 264 #define PHYS_SDRAM_1_SIZE                       0x08000000 /* 128 MB */
 265 #define PHYS_SDRAM_2_SIZE                       0x08000000 /* 128 MB */
 266 #endif
 267
 268 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
 269 /* micron 256MB */
 270 #define PHYS_SDRAM_1_SIZE                       0x10000000 /* 256 MB */
 271 #define PHYS_SDRAM_2_SIZE                       0x10000000 /* 256 MB */
 272 #endif
 273
 274 #endif /* __CONFIG_H */