include/configs/amcore.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Sysam AMCORE board configuration
   4  *
   5  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
   6  */
   7
   8 #ifndef __AMCORE_CONFIG_H
   9 #define __AMCORE_CONFIG_H
  10
  11 #define CONFIG_HOSTNAME                 "AMCORE"
  12
  13 #define CONFIG_SYS_UART_PORT            0
  14
  15 #define CONFIG_EXTRA_ENV_SETTINGS                               \
  16         "upgrade_uboot=loady; "                                 \
  17                 "protect off 0xffc00000 0xffc1ffff; "           \
  18                 "erase 0xffc00000 0xffc1ffff; "                 \
  19                 "cp.b 0x20000 0xffc00000 ${filesize}\0"         \
  20         "upgrade_kernel=loady; "                                \
  21                 "erase 0xffc20000 0xffefffff; "                 \
  22                 "cp.b 0x20000 0xffc20000 ${filesize}\0"         \
  23         "upgrade_jffs2=loady; "                                 \
  24                 "erase 0xfff00000 0xffffffff; "                 \
  25                 "cp.b 0x20000 0xfff00000 ${filesize}\0"
  26
  27 #define CONFIG_SYS_CLK                  45000000
  28 #define CONFIG_SYS_CPU_CLK              (CONFIG_SYS_CLK * 2)
  29 /* Register Base Addrs */
  30 #define CONFIG_SYS_MBAR                 0x10000000
  31 /* Definitions for initial stack pointer and data area (in DPRAM) */
  32 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  33 /* size of internal SRAM */
  34 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
  35
  36 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  37 #define CONFIG_SYS_SDRAM_SIZE           0x1000000
  38 #define CONFIG_SYS_FLASH_BASE           0xffc00000
  39 #define CONFIG_SYS_MAX_FLASH_SECT       1024
  40 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
  41
  42 /* amcore design has flash data bytes wired swapped */
  43 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  44 /* reserve 128-4KB */
  45 #define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
  46
  47 #define LDS_BOARD_TEXT \
  48         . = DEFINED(env_offset) ? env_offset : .; \
  49         env/embedded.o(.text*);
  50
  51 /* memory map space for linux boot data */
  52 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
  53
  54 /*
  55  * Cache Configuration
  56  *
  57  * Special 8K version 3 core cache.
  58  * This is a single unified instruction/data cache.
  59  * sdram - single region - no masks
  60  */
  61
  62 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  63                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
  64 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  65                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
  66 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
  67 #define CONFIG_SYS_CACHE_ACR0           (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
  68                                          CF_ACR_EN)
  69 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_DCM_P | CF_CACR_ESB | \
  70                                          CF_CACR_EC)
  71
  72 /* CS0 - AMD Flash, address 0xffc00000 */
  73 #define CONFIG_SYS_CS0_BASE             (CONFIG_SYS_FLASH_BASE>>16)
  74 /* 4MB, AA=0,V=1  C/I BIT for errata */
  75 #define CONFIG_SYS_CS0_MASK             0x003f0001
  76 /* WS=10, AA=1, PS=16bit (10) */
  77 #define CONFIG_SYS_CS0_CTRL             0x1980
  78 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
  79 #define CONFIG_SYS_CS1_BASE             0x3000
  80 #define CONFIG_SYS_CS1_MASK             0x00070001
  81 #define CONFIG_SYS_CS1_CTRL             0x0100
  82
  83 #endif  /* __AMCORE_CONFIG_H */