include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19
  20 #include <asm/arch/cpu.h>               /* get chip and board defs */
  21 #include <asm/arch/omap.h>
  22
  23 /* Clock Defines */
  24 #define V_OSCK                  26000000        /* Clock output from T2 */
  25 #define V_SCLK                  (V_OSCK >> 1)
  26
  27 #define CONFIG_MISC_INIT_R
  28
  29 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  30 #define CONFIG_SETUP_MEMORY_TAGS        1
  31 #define CONFIG_INITRD_TAG               1
  32 #define CONFIG_REVISION_TAG             1
  33
  34 /*
  35  * Size of malloc() pool
  36  */
  37 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  38 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  39                                                 /* initial data */
  40 /*
  41  * DDR related
  42  */
  43 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  44
  45 /*
  46  * Hardware drivers
  47  */
  48
  49 /*
  50  * NS16550 Configuration
  51  */
  52 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  53
  54 #define CONFIG_SYS_NS16550_SERIAL
  55 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  56 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  57
  58 /*
  59  * select serial console configuration
  60  */
  61 #define CONFIG_CONS_INDEX               3
  62 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  63 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  64
  65 /* allow to overwrite serial and ethaddr */
  66 #define CONFIG_ENV_OVERWRITE
  67 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  68                                         115200}
  69
  70 /*
  71  * USB configuration
  72  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  73  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  74  */
  75
  76 #ifdef CONFIG_USB_AM35X
  77
  78 #ifdef CONFIG_USB_MUSB_HCD
  79
  80 #ifdef CONFIG_USB_KEYBOARD
  81 #define CONFIG_PREBOOT "usb start"
  82 #endif /* CONFIG_USB_KEYBOARD */
  83
  84 #endif /* CONFIG_USB_MUSB_HCD */
  85
  86 #ifdef CONFIG_USB_MUSB_UDC
  87 /* USB device configuration */
  88 #define CONFIG_USB_DEVICE               1
  89 #define CONFIG_USB_TTY                  1
  90 /* Change these to suit your needs */
  91 #define CONFIG_USBD_VENDORID            0x0451
  92 #define CONFIG_USBD_PRODUCTID           0x5678
  93 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
  94 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
  95 #endif /* CONFIG_USB_MUSB_UDC */
  96
  97 #endif /* CONFIG_USB_AM35X */
  98
  99 #define CONFIG_SYS_I2C
 100
 101 /*
 102  * Board NAND Info.
 103  */
 104 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 105                                                         /* to access nand */
 106 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 107                                                         /* to access */
 108                                                         /* nand at CS0 */
 109
 110 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 111                                                         /* NAND devices */
 112
 113 #define CONFIG_JFFS2_NAND
 114 /* nand device jffs2 lives on */
 115 #define CONFIG_JFFS2_DEV                "nand0"
 116 /* start of jffs2 partition */
 117 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 118 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 119
 120 /* Environment information */
 121
 122 #define CONFIG_BOOTFILE         "uImage"
 123
 124 #define CONFIG_EXTRA_ENV_SETTINGS \
 125         "loadaddr=0x82000000\0" \
 126         "console=ttyS2,115200n8\0" \
 127         "mmcdev=0\0" \
 128         "mmcargs=setenv bootargs console=${console} " \
 129                 "root=/dev/mmcblk0p2 rw " \
 130                 "rootfstype=ext3 rootwait\0" \
 131         "nandargs=setenv bootargs console=${console} " \
 132                 "root=/dev/mtdblock4 rw " \
 133                 "rootfstype=jffs2\0" \
 134         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 135         "bootscript=echo Running bootscript from mmc ...; " \
 136                 "source ${loadaddr}\0" \
 137         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 138         "mmcboot=echo Booting from mmc ...; " \
 139                 "run mmcargs; " \
 140                 "bootm ${loadaddr}\0" \
 141         "nandboot=echo Booting from nand ...; " \
 142                 "run nandargs; " \
 143                 "nand read ${loadaddr} 280000 400000; " \
 144                 "bootm ${loadaddr}\0" \
 145
 146 #define CONFIG_BOOTCOMMAND \
 147         "mmc dev ${mmcdev}; if mmc rescan; then " \
 148                 "if run loadbootscript; then " \
 149                         "run bootscript; " \
 150                 "else " \
 151                         "if run loaduimage; then " \
 152                                 "run mmcboot; " \
 153                         "else run nandboot; " \
 154                         "fi; " \
 155                 "fi; " \
 156         "else run nandboot; fi"
 157
 158 /*
 159  * Miscellaneous configurable options
 160  */
 161 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 162 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 163                                                 /* args */
 164 /* memtest works on */
 165 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 166 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 167                                         0x01F00000) /* 31MB */
 168
 169 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 170                                                                 /* address */
 171
 172 /*
 173  * AM3517 has 12 GP timers, they can be driven by the system clock
 174  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 175  * This rate is divided by a local divisor.
 176  */
 177 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 178 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 179
 180 /*-----------------------------------------------------------------------
 181  * Physical Memory Map
 182  */
 183 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 184 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 185 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 186
 187 /*-----------------------------------------------------------------------
 188  * FLASH and environment organization
 189  */
 190
 191 /* **** PISMO SUPPORT *** */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 193                                                 /* on one chip */
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 195 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 196
 197 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 198
 199 /* Monitor at start of flash */
 200 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 201
 202 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 203 #define CONFIG_ENV_OFFSET               0x260000
 204 #define CONFIG_ENV_ADDR                 0x260000
 205
 206 /*-----------------------------------------------------------------------
 207  * CFI FLASH driver setup
 208  */
 209 /* timeout values are in ticks */
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 212
 213 /* Flash banks JFFS2 should use */
 214 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 215                                         CONFIG_SYS_MAX_NAND_DEVICE)
 216 #define CONFIG_SYS_JFFS2_MEM_NAND
 217 /* use flash_info[2] */
 218 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 219 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 220
 221 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 223 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 224 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 225                                          CONFIG_SYS_INIT_RAM_SIZE - \
 226                                          GENERATED_GBL_DATA_SIZE)
 227
 228 /* Defines for SPL */
 229 #define CONFIG_SPL_TEXT_BASE            0x40200800
 230 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 231                                          CONFIG_SPL_TEXT_BASE)
 232
 233 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 234 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 235
 236 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 237 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 238
 239 #define CONFIG_SPL_NAND_BASE
 240 #define CONFIG_SPL_NAND_DRIVERS
 241 #define CONFIG_SPL_NAND_ECC
 242
 243 /* NAND boot config */
 244 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 245 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 246 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 247 #define CONFIG_SYS_NAND_OOBSIZE         64
 248 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 249 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 250 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 251                                                 10, 11, 12, 13}
 252 #define CONFIG_SYS_NAND_ECCSIZE         512
 253 #define CONFIG_SYS_NAND_ECCBYTES        3
 254 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 255 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 256 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 257
 258 /*
 259  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 260  * 64 bytes before this address should be set aside for u-boot.img's
 261  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 262  * other needs.
 263  */
 264 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 265 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 266
 267 #endif /* __CONFIG_H */