include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  20
  21 #include <asm/arch/cpu.h>               /* get chip and board defs */
  22 #include <asm/arch/omap.h>
  23
  24 /* Clock Defines */
  25 #define V_OSCK                  26000000        /* Clock output from T2 */
  26 #define V_SCLK                  (V_OSCK >> 1)
  27
  28 #define CONFIG_MISC_INIT_R
  29
  30 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  31 #define CONFIG_SETUP_MEMORY_TAGS        1
  32 #define CONFIG_INITRD_TAG               1
  33 #define CONFIG_REVISION_TAG             1
  34
  35 /*
  36  * Size of malloc() pool
  37  */
  38 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  39 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  40                                                 /* initial data */
  41 /*
  42  * DDR related
  43  */
  44 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  45
  46 /*
  47  * Hardware drivers
  48  */
  49
  50 /*
  51  * NS16550 Configuration
  52  */
  53 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  54
  55 #define CONFIG_SYS_NS16550_SERIAL
  56 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  57 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  58
  59 /*
  60  * select serial console configuration
  61  */
  62 #define CONFIG_CONS_INDEX               3
  63 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  64 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  65
  66 /* allow to overwrite serial and ethaddr */
  67 #define CONFIG_ENV_OVERWRITE
  68 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  69                                         115200}
  70
  71 /*
  72  * USB configuration
  73  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  74  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  75  */
  76 #define CONFIG_USB_AM35X                1
  77 #define CONFIG_USB_MUSB_HCD                     1
  78
  79 #ifdef CONFIG_USB_AM35X
  80
  81 #ifdef CONFIG_USB_MUSB_HCD
  82
  83 #ifdef CONFIG_USB_KEYBOARD
  84 #define CONFIG_SYS_USB_EVENT_POLL
  85 #define CONFIG_PREBOOT "usb start"
  86 #endif /* CONFIG_USB_KEYBOARD */
  87
  88 #endif /* CONFIG_USB_MUSB_HCD */
  89
  90 #ifdef CONFIG_USB_MUSB_UDC
  91 /* USB device configuration */
  92 #define CONFIG_USB_DEVICE               1
  93 #define CONFIG_USB_TTY                  1
  94 /* Change these to suit your needs */
  95 #define CONFIG_USBD_VENDORID            0x0451
  96 #define CONFIG_USBD_PRODUCTID           0x5678
  97 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
  98 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
  99 #endif /* CONFIG_USB_MUSB_UDC */
 100
 101 #endif /* CONFIG_USB_AM35X */
 102
 103 #define CONFIG_SYS_I2C
 104 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 105 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 106
 107 /*
 108  * Board NAND Info.
 109  */
 110 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 111                                                         /* to access nand */
 112 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 113                                                         /* to access */
 114                                                         /* nand at CS0 */
 115
 116 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 117                                                         /* NAND devices */
 118
 119 #define CONFIG_JFFS2_NAND
 120 /* nand device jffs2 lives on */
 121 #define CONFIG_JFFS2_DEV                "nand0"
 122 /* start of jffs2 partition */
 123 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 124 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 125
 126 /* Environment information */
 127
 128 #define CONFIG_BOOTFILE         "uImage"
 129
 130 #define CONFIG_EXTRA_ENV_SETTINGS \
 131         "loadaddr=0x82000000\0" \
 132         "console=ttyS2,115200n8\0" \
 133         "mmcdev=0\0" \
 134         "mmcargs=setenv bootargs console=${console} " \
 135                 "root=/dev/mmcblk0p2 rw " \
 136                 "rootfstype=ext3 rootwait\0" \
 137         "nandargs=setenv bootargs console=${console} " \
 138                 "root=/dev/mtdblock4 rw " \
 139                 "rootfstype=jffs2\0" \
 140         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 141         "bootscript=echo Running bootscript from mmc ...; " \
 142                 "source ${loadaddr}\0" \
 143         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 144         "mmcboot=echo Booting from mmc ...; " \
 145                 "run mmcargs; " \
 146                 "bootm ${loadaddr}\0" \
 147         "nandboot=echo Booting from nand ...; " \
 148                 "run nandargs; " \
 149                 "nand read ${loadaddr} 280000 400000; " \
 150                 "bootm ${loadaddr}\0" \
 151
 152 #define CONFIG_BOOTCOMMAND \
 153         "mmc dev ${mmcdev}; if mmc rescan; then " \
 154                 "if run loadbootscript; then " \
 155                         "run bootscript; " \
 156                 "else " \
 157                         "if run loaduimage; then " \
 158                                 "run mmcboot; " \
 159                         "else run nandboot; " \
 160                         "fi; " \
 161                 "fi; " \
 162         "else run nandboot; fi"
 163
 164 #define CONFIG_AUTO_COMPLETE    1
 165 /*
 166  * Miscellaneous configurable options
 167  */
 168 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 169 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 170 /* Print Buffer Size */
 171 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 172                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 173 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 174                                                 /* args */
 175 /* Boot Argument Buffer Size */
 176 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 177 /* memtest works on */
 178 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 179 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 180                                         0x01F00000) /* 31MB */
 181
 182 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 183                                                                 /* address */
 184
 185 /*
 186  * AM3517 has 12 GP timers, they can be driven by the system clock
 187  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 188  * This rate is divided by a local divisor.
 189  */
 190 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 191 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 192
 193 /*-----------------------------------------------------------------------
 194  * Physical Memory Map
 195  */
 196 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 197 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 198 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 199
 200 /*-----------------------------------------------------------------------
 201  * FLASH and environment organization
 202  */
 203
 204 /* **** PISMO SUPPORT *** */
 205 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 206                                                 /* on one chip */
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 208 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 209
 210 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 211
 212 /* Monitor at start of flash */
 213 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 214
 215 #define CONFIG_NAND_OMAP_GPMC
 216 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 217
 218 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 219 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 220 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 221
 222 /*-----------------------------------------------------------------------
 223  * CFI FLASH driver setup
 224  */
 225 /* timeout values are in ticks */
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 228
 229 /* Flash banks JFFS2 should use */
 230 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 231                                         CONFIG_SYS_MAX_NAND_DEVICE)
 232 #define CONFIG_SYS_JFFS2_MEM_NAND
 233 /* use flash_info[2] */
 234 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 235 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 236
 237 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 238 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 239 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 240 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 241                                          CONFIG_SYS_INIT_RAM_SIZE - \
 242                                          GENERATED_GBL_DATA_SIZE)
 243
 244 /* Defines for SPL */
 245 #define CONFIG_SPL_FRAMEWORK
 246 #define CONFIG_SPL_NAND_SIMPLE
 247 #define CONFIG_SPL_TEXT_BASE            0x40200800
 248 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 249                                          CONFIG_SPL_TEXT_BASE)
 250
 251 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 252 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 253
 254 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 255 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 256
 257 #define CONFIG_SPL_NAND_BASE
 258 #define CONFIG_SPL_NAND_DRIVERS
 259 #define CONFIG_SPL_NAND_ECC
 260
 261 /* NAND boot config */
 262 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 263 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 264 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 265 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 266 #define CONFIG_SYS_NAND_OOBSIZE         64
 267 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 268 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 269 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 270                                                 10, 11, 12, 13}
 271 #define CONFIG_SYS_NAND_ECCSIZE         512
 272 #define CONFIG_SYS_NAND_ECCBYTES        3
 273 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 274 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 275 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 276
 277 /*
 278  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 279  * 64 bytes before this address should be set aside for u-boot.img's
 280  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 281  * other needs.
 282  */
 283 #define CONFIG_SYS_TEXT_BASE            0x80100000
 284 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 285 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 286
 287 #endif /* __CONFIG_H */