include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  20 #define CONFIG_OMAP3_AM3517CRANE        1       /* working with CRANEBOARD */
  21 #define CONFIG_OMAP_COMMON
  22 /* Common ARM Erratas */
  23 #define CONFIG_ARM_ERRATA_454179
  24 #define CONFIG_ARM_ERRATA_430973
  25 #define CONFIG_ARM_ERRATA_621766
  26
  27 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  28
  29 #include <asm/arch/cpu.h>               /* get chip and board defs */
  30 #include <asm/arch/omap.h>
  31
  32 /*
  33  * Display CPU and Board information
  34  */
  35 #define CONFIG_DISPLAY_BOARDINFO        1
  36
  37 /* Clock Defines */
  38 #define V_OSCK                  26000000        /* Clock output from T2 */
  39 #define V_SCLK                  (V_OSCK >> 1)
  40
  41 #define CONFIG_MISC_INIT_R
  42
  43 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  44 #define CONFIG_SETUP_MEMORY_TAGS        1
  45 #define CONFIG_INITRD_TAG               1
  46 #define CONFIG_REVISION_TAG             1
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  52 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  53                                                 /* initial data */
  54 /*
  55  * DDR related
  56  */
  57 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  58
  59 /*
  60  * Hardware drivers
  61  */
  62
  63 /*
  64  * NS16550 Configuration
  65  */
  66 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  67
  68 #define CONFIG_SYS_NS16550_SERIAL
  69 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  70 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  71
  72 /*
  73  * select serial console configuration
  74  */
  75 #define CONFIG_CONS_INDEX               3
  76 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  77 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  78
  79 /* allow to overwrite serial and ethaddr */
  80 #define CONFIG_ENV_OVERWRITE
  81 #define CONFIG_BAUDRATE                 115200
  82 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  83                                         115200}
  84 #define CONFIG_GENERIC_MMC              1
  85 #define CONFIG_MMC                      1
  86 #define CONFIG_OMAP_HSMMC               1
  87 #define CONFIG_DOS_PARTITION            1
  88
  89 /*
  90  * USB configuration
  91  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  92  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  93  */
  94 #define CONFIG_USB_AM35X                1
  95 #define CONFIG_USB_MUSB_HCD                     1
  96
  97 #ifdef CONFIG_USB_AM35X
  98
  99 #ifdef CONFIG_USB_MUSB_HCD
 100
 101 #define CONGIG_CMD_STORAGE
 102
 103 #ifdef CONFIG_USB_KEYBOARD
 104 #define CONFIG_SYS_USB_EVENT_POLL
 105 #define CONFIG_PREBOOT "usb start"
 106 #endif /* CONFIG_USB_KEYBOARD */
 107
 108 #endif /* CONFIG_USB_MUSB_HCD */
 109
 110 #ifdef CONFIG_USB_MUSB_UDC
 111 /* USB device configuration */
 112 #define CONFIG_USB_DEVICE               1
 113 #define CONFIG_USB_TTY                  1
 114 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 115 /* Change these to suit your needs */
 116 #define CONFIG_USBD_VENDORID            0x0451
 117 #define CONFIG_USBD_PRODUCTID           0x5678
 118 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
 119 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
 120 #endif /* CONFIG_USB_MUSB_UDC */
 121
 122 #endif /* CONFIG_USB_AM35X */
 123
 124 /* commands to include */
 125 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 126
 127 #define CONFIG_CMD_NAND         /* NAND support                 */
 128
 129 #define CONFIG_SYS_NO_FLASH
 130 #define CONFIG_SYS_I2C
 131 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 132 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 133 #define CONFIG_SYS_I2C_OMAP34XX
 134
 135 /*
 136  * Board NAND Info.
 137  */
 138 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 139                                                         /* to access nand */
 140 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 141                                                         /* to access */
 142                                                         /* nand at CS0 */
 143
 144 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 145                                                         /* NAND devices */
 146
 147 #define CONFIG_JFFS2_NAND
 148 /* nand device jffs2 lives on */
 149 #define CONFIG_JFFS2_DEV                "nand0"
 150 /* start of jffs2 partition */
 151 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 152 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 153
 154 /* Environment information */
 155
 156 #define CONFIG_BOOTFILE         "uImage"
 157
 158 #define CONFIG_EXTRA_ENV_SETTINGS \
 159         "loadaddr=0x82000000\0" \
 160         "console=ttyS2,115200n8\0" \
 161         "mmcdev=0\0" \
 162         "mmcargs=setenv bootargs console=${console} " \
 163                 "root=/dev/mmcblk0p2 rw " \
 164                 "rootfstype=ext3 rootwait\0" \
 165         "nandargs=setenv bootargs console=${console} " \
 166                 "root=/dev/mtdblock4 rw " \
 167                 "rootfstype=jffs2\0" \
 168         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 169         "bootscript=echo Running bootscript from mmc ...; " \
 170                 "source ${loadaddr}\0" \
 171         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 172         "mmcboot=echo Booting from mmc ...; " \
 173                 "run mmcargs; " \
 174                 "bootm ${loadaddr}\0" \
 175         "nandboot=echo Booting from nand ...; " \
 176                 "run nandargs; " \
 177                 "nand read ${loadaddr} 280000 400000; " \
 178                 "bootm ${loadaddr}\0" \
 179
 180 #define CONFIG_BOOTCOMMAND \
 181         "mmc dev ${mmcdev}; if mmc rescan; then " \
 182                 "if run loadbootscript; then " \
 183                         "run bootscript; " \
 184                 "else " \
 185                         "if run loaduimage; then " \
 186                                 "run mmcboot; " \
 187                         "else run nandboot; " \
 188                         "fi; " \
 189                 "fi; " \
 190         "else run nandboot; fi"
 191
 192 #define CONFIG_AUTO_COMPLETE    1
 193 /*
 194  * Miscellaneous configurable options
 195  */
 196 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 197 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 198 /* Print Buffer Size */
 199 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 200                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 201 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 202                                                 /* args */
 203 /* Boot Argument Buffer Size */
 204 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 205 /* memtest works on */
 206 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 207 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 208                                         0x01F00000) /* 31MB */
 209
 210 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 211                                                                 /* address */
 212
 213 /*
 214  * AM3517 has 12 GP timers, they can be driven by the system clock
 215  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 216  * This rate is divided by a local divisor.
 217  */
 218 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 219 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 220
 221 /*-----------------------------------------------------------------------
 222  * Physical Memory Map
 223  */
 224 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 225 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 226 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 227
 228 /*-----------------------------------------------------------------------
 229  * FLASH and environment organization
 230  */
 231
 232 /* **** PISMO SUPPORT *** */
 233 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 234                                                 /* on one chip */
 235 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 236 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 237
 238 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 239
 240 /* Monitor at start of flash */
 241 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 242
 243 #define CONFIG_NAND_OMAP_GPMC
 244 #define CONFIG_ENV_IS_IN_NAND           1
 245 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 246
 247 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 248 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 249 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 250
 251 /*-----------------------------------------------------------------------
 252  * CFI FLASH driver setup
 253  */
 254 /* timeout values are in ticks */
 255 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 256 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 257
 258 /* Flash banks JFFS2 should use */
 259 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 260                                         CONFIG_SYS_MAX_NAND_DEVICE)
 261 #define CONFIG_SYS_JFFS2_MEM_NAND
 262 /* use flash_info[2] */
 263 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 264 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 265
 266 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 267 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 268 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 269 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 270                                          CONFIG_SYS_INIT_RAM_SIZE - \
 271                                          GENERATED_GBL_DATA_SIZE)
 272
 273 /* Defines for SPL */
 274 #define CONFIG_SPL_FRAMEWORK
 275 #define CONFIG_SPL_BOARD_INIT
 276 #define CONFIG_SPL_NAND_SIMPLE
 277 #define CONFIG_SPL_TEXT_BASE            0x40200800
 278 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 279                                          CONFIG_SPL_TEXT_BASE)
 280
 281 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 282 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 283
 284 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 285 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 286 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 287 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 288
 289 #define CONFIG_SPL_NAND_BASE
 290 #define CONFIG_SPL_NAND_DRIVERS
 291 #define CONFIG_SPL_NAND_ECC
 292 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 293
 294 /* NAND boot config */
 295 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 296 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 297 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 298 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 299 #define CONFIG_SYS_NAND_OOBSIZE         64
 300 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 301 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 302 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 303                                                 10, 11, 12, 13}
 304 #define CONFIG_SYS_NAND_ECCSIZE         512
 305 #define CONFIG_SYS_NAND_ECCBYTES        3
 306 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 307 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 308 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 309
 310 /*
 311  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 312  * 64 bytes before this address should be set aside for u-boot.img's
 313  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 314  * other needs.
 315  */
 316 #define CONFIG_SYS_TEXT_BASE            0x80100000
 317 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 318 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 319
 320 #endif /* __CONFIG_H */