include/configs/adp-ag101p.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ag101/ag101.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  19 #define CONFIG_MEM_REMAP
  20 #endif
  21
  22 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  23 #ifdef CONFIG_OF_CONTROL
  24 #undef CONFIG_OF_SEPARATE
  25 #endif
  26 #endif
  27
  28 /*
  29  * Timer
  30  */
  31 #define VERSION_CLOCK           get_board_sys_clk()
  32
  33 /*
  34  * Use Externel CLOCK or PCLK
  35  */
  36 #undef CONFIG_FTRTC010_EXTCLK
  37
  38 #ifndef CONFIG_FTRTC010_EXTCLK
  39 #define CONFIG_FTRTC010_PCLK
  40 #endif
  41
  42 #ifdef CONFIG_FTRTC010_EXTCLK
  43 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  44 #else
  45 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  46 #endif
  47
  48 #define TIMER_LOAD_VAL  0xffffffff
  49
  50 /*
  51  * Real Time Clock
  52  */
  53 #define CONFIG_RTC_FTRTC010
  54
  55 /*
  56  * Real Time Clock Divider
  57  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  58  */
  59 #define OSC_5MHZ                        (5*1000000)
  60 #define OSC_CLK                         (4*OSC_5MHZ)
  61 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  62
  63 /*
  64  * Serial console configuration
  65  */
  66
  67 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  68 #define CONFIG_SYS_NS16550_SERIAL
  69 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  70 #ifndef CONFIG_DM_SERIAL
  71 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  72 #endif
  73 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  74
  75 /*
  76  * Miscellaneous configurable options
  77  */
  78
  79 /*
  80  * AHB Controller configuration
  81  */
  82 #define CONFIG_FTAHBC020S
  83
  84 #ifdef CONFIG_FTAHBC020S
  85 #include <faraday/ftahbc020s.h>
  86
  87 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  88 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
  89
  90 /*
  91  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  92  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  93  * in C language.
  94  */
  95 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  96         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  97                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  98 #endif
  99
 100 /*
 101  * Watchdog
 102  */
 103 #define CONFIG_FTWDT010_WATCHDOG
 104
 105 /*
 106  * PMU Power controller configuration
 107  */
 108 #define CONFIG_PMU
 109 #define CONFIG_FTPMU010_POWER
 110
 111 #ifdef CONFIG_FTPMU010_POWER
 112 #include <faraday/ftpmu010.h>
 113 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 114 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 115                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 116                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 117                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 118                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 119                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 120                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 121 #endif
 122
 123 /*
 124  * SDRAM controller configuration
 125  */
 126 #define CONFIG_FTSDMC021
 127
 128 #ifdef CONFIG_FTSDMC021
 129 #include <faraday/ftsdmc021.h>
 130
 131 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 132                                          FTSDMC021_TP1_TRP(1)   |       \
 133                                          FTSDMC021_TP1_TRCD(1)  |       \
 134                                          FTSDMC021_TP1_TRF(3)   |       \
 135                                          FTSDMC021_TP1_TWR(1)   |       \
 136                                          FTSDMC021_TP1_TCL(2))
 137
 138 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 139                                          FTSDMC021_TP2_INI_REFT(8) |    \
 140                                          FTSDMC021_TP2_REF_INTV(0x180))
 141
 142 /*
 143  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 144  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 145  * C language.
 146  */
 147 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 148                                          FTSDMC021_CR1_DSZ(3)    |      \
 149                                          FTSDMC021_CR1_MBW(2)    |      \
 150                                          FTSDMC021_CR1_BNKSIZE(6))
 151
 152 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 153                                          FTSDMC021_CR2_IREF      |      \
 154                                          FTSDMC021_CR2_ISMR)
 155
 156 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 157 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 158                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 159
 160 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 161         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 162 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 163                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 164 #endif
 165
 166 /*
 167  * Physical Memory Map
 168  */
 169 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 170 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 171 #else
 172 #ifdef CONFIG_MEM_REMAP
 173 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 174 #else
 175 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 176 #endif
 177 #endif
 178
 179 #define PHYS_SDRAM_1 \
 180         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 181
 182 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 183 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 184 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 185 #else
 186 #ifdef CONFIG_MEM_REMAP
 187 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 188 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 189 #else
 190 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 191 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 192 #endif
 193 #endif
 194
 195 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 196
 197 #ifdef CONFIG_MEM_REMAP
 198 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 199                                         GENERATED_GBL_DATA_SIZE)
 200 #else
 201 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 202                                         GENERATED_GBL_DATA_SIZE)
 203 #endif /* CONFIG_MEM_REMAP */
 204
 205 /*
 206  * Static memory controller configuration
 207  */
 208 #define CONFIG_FTSMC020
 209
 210 #ifdef CONFIG_FTSMC020
 211 #include <faraday/ftsmc020.h>
 212
 213 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 214         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 215         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 216 }
 217
 218 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 219 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 220                                          FTSMC020_BANK_SIZE_32M |       \
 221                                          FTSMC020_BANK_MBW_32)
 222
 223 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 224                                          FTSMC020_TPR_AST(1)    |       \
 225                                          FTSMC020_TPR_CTW(1)    |       \
 226                                          FTSMC020_TPR_ATI(1)    |       \
 227                                          FTSMC020_TPR_AT2(1)    |       \
 228                                          FTSMC020_TPR_WTC(1)    |       \
 229                                          FTSMC020_TPR_AHT(1)    |       \
 230                                          FTSMC020_TPR_TRNA(1))
 231 #endif
 232
 233 /*
 234  * FLASH on ADP_AG101P is connected to BANK0
 235  * Just disalbe the other BANK to avoid detection error.
 236  */
 237 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 238                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 239                                  FTSMC020_BANK_SIZE_32M           |     \
 240                                  FTSMC020_BANK_MBW_32)
 241
 242 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 243                                  FTSMC020_TPR_CTW(3)   |        \
 244                                  FTSMC020_TPR_ATI(0xf) |        \
 245                                  FTSMC020_TPR_AT2(3)   |        \
 246                                  FTSMC020_TPR_WTC(3)   |        \
 247                                  FTSMC020_TPR_AHT(3)   |        \
 248                                  FTSMC020_TPR_TRNA(0xf))
 249
 250 #define FTSMC020_BANK1_CONFIG   (0x00)
 251 #define FTSMC020_BANK1_TIMING   (0x00)
 252 #endif /* CONFIG_FTSMC020 */
 253
 254 /*
 255  * FLASH and environment organization
 256  */
 257 /* use CFI framework */
 258
 259 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 260 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 261
 262 /* support JEDEC */
 263
 264 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 265 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 266 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 267 #else
 268 #ifdef CONFIG_MEM_REMAP
 269 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 270 #else
 271 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 272 #endif
 273 #endif  /* CONFIG_MEM_REMAP */
 274
 275 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 276 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 277 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 278
 279 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 280 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 281
 282 /* max number of memory banks */
 283 /*
 284  * There are 4 banks supported for this Controller,
 285  * but we have only 1 bank connected to flash on board
 286  */
 287 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 288 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 289 #endif
 290 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 291
 292 /* max number of sectors on one chip */
 293 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 294 #define CONFIG_SYS_MAX_FLASH_SECT       512
 295
 296 /* environments */
 297
 298 /*
 299  * For booting Linux, the board info and command line data
 300  * have to be in the first 16 MB of memory, since this is
 301  * the maximum mapped by the Linux kernel during initialization.
 302  */
 303
 304 /* Initial Memory map for Linux*/
 305 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 306 /* Increase max gunzip size */
 307 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 308
 309 #endif  /* __CONFIG_H */