include/configs/adp-ag101p.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ag101/ag101.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_USE_INTERRUPT
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_ARCH_MAP_SYSMEM
  22
  23 #define CONFIG_BOOTP_SEND_HOSTNAME
  24 #define CONFIG_BOOTP_SERVERIP
  25
  26 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  27 #define CONFIG_MEM_REMAP
  28 #endif
  29
  30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  31 #ifdef CONFIG_OF_CONTROL
  32 #undef CONFIG_OF_SEPARATE
  33 #define CONFIG_OF_EMBED
  34 #endif
  35 #endif
  36
  37 /*
  38  * Timer
  39  */
  40 #define CONFIG_SYS_CLK_FREQ     39062500
  41 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  42
  43 /*
  44  * Use Externel CLOCK or PCLK
  45  */
  46 #undef CONFIG_FTRTC010_EXTCLK
  47
  48 #ifndef CONFIG_FTRTC010_EXTCLK
  49 #define CONFIG_FTRTC010_PCLK
  50 #endif
  51
  52 #ifdef CONFIG_FTRTC010_EXTCLK
  53 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  54 #else
  55 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  56 #endif
  57
  58 #define TIMER_LOAD_VAL  0xffffffff
  59
  60 /*
  61  * Real Time Clock
  62  */
  63 #define CONFIG_RTC_FTRTC010
  64
  65 /*
  66  * Real Time Clock Divider
  67  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  68  */
  69 #define OSC_5MHZ                        (5*1000000)
  70 #define OSC_CLK                         (4*OSC_5MHZ)
  71 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  72
  73 /*
  74  * Serial console configuration
  75  */
  76
  77 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  78 #define CONFIG_SYS_NS16550_SERIAL
  79 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  80 #ifndef CONFIG_DM_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  82 #endif
  83 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  84
  85 /*
  86  * SD (MMC) controller
  87  */
  88 #define CONFIG_FTSDC010_SDIO
  89
  90 /*
  91  * Miscellaneous configurable options
  92  */
  93
  94 /*
  95  * Size of malloc() pool
  96  */
  97 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  98 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
  99
 100 /*
 101  * AHB Controller configuration
 102  */
 103 #define CONFIG_FTAHBC020S
 104
 105 #ifdef CONFIG_FTAHBC020S
 106 #include <faraday/ftahbc020s.h>
 107
 108 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
 109 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
 110
 111 /*
 112  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
 113  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
 114  * in C language.
 115  */
 116 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 117         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 118                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 119 #endif
 120
 121 /*
 122  * Watchdog
 123  */
 124 #define CONFIG_FTWDT010_WATCHDOG
 125
 126 /*
 127  * PMU Power controller configuration
 128  */
 129 #define CONFIG_PMU
 130 #define CONFIG_FTPMU010_POWER
 131
 132 #ifdef CONFIG_FTPMU010_POWER
 133 #include <faraday/ftpmu010.h>
 134 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 135 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 136                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 137                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 138                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 139                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 140                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 141                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 142 #endif
 143
 144 /*
 145  * SDRAM controller configuration
 146  */
 147 #define CONFIG_FTSDMC021
 148
 149 #ifdef CONFIG_FTSDMC021
 150 #include <faraday/ftsdmc021.h>
 151
 152 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 153                                          FTSDMC021_TP1_TRP(1)   |       \
 154                                          FTSDMC021_TP1_TRCD(1)  |       \
 155                                          FTSDMC021_TP1_TRF(3)   |       \
 156                                          FTSDMC021_TP1_TWR(1)   |       \
 157                                          FTSDMC021_TP1_TCL(2))
 158
 159 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 160                                          FTSDMC021_TP2_INI_REFT(8) |    \
 161                                          FTSDMC021_TP2_REF_INTV(0x180))
 162
 163 /*
 164  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 165  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 166  * C language.
 167  */
 168 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 169                                          FTSDMC021_CR1_DSZ(3)    |      \
 170                                          FTSDMC021_CR1_MBW(2)    |      \
 171                                          FTSDMC021_CR1_BNKSIZE(6))
 172
 173 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 174                                          FTSDMC021_CR2_IREF      |      \
 175                                          FTSDMC021_CR2_ISMR)
 176
 177 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 178 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 179                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 180
 181 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 182         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 183 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 184                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 185 #endif
 186
 187 /*
 188  * Physical Memory Map
 189  */
 190 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 191 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 192 #else
 193 #ifdef CONFIG_MEM_REMAP
 194 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 195 #else
 196 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 197 #endif
 198 #endif
 199
 200 #define PHYS_SDRAM_1 \
 201         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 202
 203 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 204
 205 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 206 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 207 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 208 #else
 209 #ifdef CONFIG_MEM_REMAP
 210 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 211 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 212 #else
 213 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 214 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 215 #endif
 216 #endif
 217
 218 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 219
 220 #ifdef CONFIG_MEM_REMAP
 221 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 222                                         GENERATED_GBL_DATA_SIZE)
 223 #else
 224 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 225                                         GENERATED_GBL_DATA_SIZE)
 226 #endif /* CONFIG_MEM_REMAP */
 227
 228 /*
 229  * Load address and memory test area should agree with
 230  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 231  */
 232 #define CONFIG_SYS_LOAD_ADDR            0x300000
 233
 234 /* memtest works on 63 MB in DRAM */
 235 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 236 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 237
 238 /*
 239  * Static memory controller configuration
 240  */
 241 #define CONFIG_FTSMC020
 242
 243 #ifdef CONFIG_FTSMC020
 244 #include <faraday/ftsmc020.h>
 245
 246 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 247         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 248         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 249 }
 250
 251 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 252 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 253                                          FTSMC020_BANK_SIZE_32M |       \
 254                                          FTSMC020_BANK_MBW_32)
 255
 256 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 257                                          FTSMC020_TPR_AST(1)    |       \
 258                                          FTSMC020_TPR_CTW(1)    |       \
 259                                          FTSMC020_TPR_ATI(1)    |       \
 260                                          FTSMC020_TPR_AT2(1)    |       \
 261                                          FTSMC020_TPR_WTC(1)    |       \
 262                                          FTSMC020_TPR_AHT(1)    |       \
 263                                          FTSMC020_TPR_TRNA(1))
 264 #endif
 265
 266 /*
 267  * FLASH on ADP_AG101P is connected to BANK0
 268  * Just disalbe the other BANK to avoid detection error.
 269  */
 270 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 271                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 272                                  FTSMC020_BANK_SIZE_32M           |     \
 273                                  FTSMC020_BANK_MBW_32)
 274
 275 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 276                                  FTSMC020_TPR_CTW(3)   |        \
 277                                  FTSMC020_TPR_ATI(0xf) |        \
 278                                  FTSMC020_TPR_AT2(3)   |        \
 279                                  FTSMC020_TPR_WTC(3)   |        \
 280                                  FTSMC020_TPR_AHT(3)   |        \
 281                                  FTSMC020_TPR_TRNA(0xf))
 282
 283 #define FTSMC020_BANK1_CONFIG   (0x00)
 284 #define FTSMC020_BANK1_TIMING   (0x00)
 285 #endif /* CONFIG_FTSMC020 */
 286
 287 /*
 288  * FLASH and environment organization
 289  */
 290 /* use CFI framework */
 291 #define CONFIG_SYS_FLASH_CFI
 292 #define CONFIG_FLASH_CFI_DRIVER
 293
 294 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 295 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 296 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 297
 298 /* support JEDEC */
 299
 300 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 301 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 302 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 303 #else
 304 #ifdef CONFIG_MEM_REMAP
 305 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 306 #else
 307 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 308 #endif
 309 #endif  /* CONFIG_MEM_REMAP */
 310
 311 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 312 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 313 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 314
 315 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 316 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 317
 318 /* max number of memory banks */
 319 /*
 320  * There are 4 banks supported for this Controller,
 321  * but we have only 1 bank connected to flash on board
 322  */
 323 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 324 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 325 #endif
 326 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 327
 328 /* max number of sectors on one chip */
 329 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 330 #define CONFIG_ENV_SECT_SIZE            CONFIG_FLASH_SECTOR_SIZE
 331 #define CONFIG_SYS_MAX_FLASH_SECT       512
 332
 333 /* environments */
 334 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + 0x140000)
 335 #define CONFIG_ENV_SIZE                 8192
 336 #define CONFIG_ENV_OVERWRITE
 337
 338 /*
 339  * For booting Linux, the board info and command line data
 340  * have to be in the first 16 MB of memory, since this is
 341  * the maximum mapped by the Linux kernel during initialization.
 342  */
 343
 344 /* Initial Memory map for Linux*/
 345 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 346 /* Increase max gunzip size */
 347 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 348
 349 #endif  /* __CONFIG_H */