include/configs/adp-ag101p.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ag101/ag101.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_ARCH_MAP_SYSMEM
  19
  20 #define CONFIG_BOOTP_SERVERIP
  21
  22 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  23 #define CONFIG_MEM_REMAP
  24 #endif
  25
  26 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  27 #ifdef CONFIG_OF_CONTROL
  28 #undef CONFIG_OF_SEPARATE
  29 #define CONFIG_OF_EMBED
  30 #endif
  31 #endif
  32
  33 /*
  34  * Timer
  35  */
  36 #define CONFIG_SYS_CLK_FREQ     39062500
  37 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  38
  39 /*
  40  * Use Externel CLOCK or PCLK
  41  */
  42 #undef CONFIG_FTRTC010_EXTCLK
  43
  44 #ifndef CONFIG_FTRTC010_EXTCLK
  45 #define CONFIG_FTRTC010_PCLK
  46 #endif
  47
  48 #ifdef CONFIG_FTRTC010_EXTCLK
  49 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  50 #else
  51 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  52 #endif
  53
  54 #define TIMER_LOAD_VAL  0xffffffff
  55
  56 /*
  57  * Real Time Clock
  58  */
  59 #define CONFIG_RTC_FTRTC010
  60
  61 /*
  62  * Real Time Clock Divider
  63  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  64  */
  65 #define OSC_5MHZ                        (5*1000000)
  66 #define OSC_CLK                         (4*OSC_5MHZ)
  67 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  68
  69 /*
  70  * Serial console configuration
  71  */
  72
  73 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  76 #ifndef CONFIG_DM_SERIAL
  77 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  78 #endif
  79 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84
  85 /*
  86  * AHB Controller configuration
  87  */
  88 #define CONFIG_FTAHBC020S
  89
  90 #ifdef CONFIG_FTAHBC020S
  91 #include <faraday/ftahbc020s.h>
  92
  93 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  94 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
  95
  96 /*
  97  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  98  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  99  * in C language.
 100  */
 101 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
 102         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
 103                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 104 #endif
 105
 106 /*
 107  * Watchdog
 108  */
 109 #define CONFIG_FTWDT010_WATCHDOG
 110
 111 /*
 112  * PMU Power controller configuration
 113  */
 114 #define CONFIG_PMU
 115 #define CONFIG_FTPMU010_POWER
 116
 117 #ifdef CONFIG_FTPMU010_POWER
 118 #include <faraday/ftpmu010.h>
 119 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 120 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 121                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 122                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 123                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 124                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 125                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 126                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 127 #endif
 128
 129 /*
 130  * SDRAM controller configuration
 131  */
 132 #define CONFIG_FTSDMC021
 133
 134 #ifdef CONFIG_FTSDMC021
 135 #include <faraday/ftsdmc021.h>
 136
 137 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 138                                          FTSDMC021_TP1_TRP(1)   |       \
 139                                          FTSDMC021_TP1_TRCD(1)  |       \
 140                                          FTSDMC021_TP1_TRF(3)   |       \
 141                                          FTSDMC021_TP1_TWR(1)   |       \
 142                                          FTSDMC021_TP1_TCL(2))
 143
 144 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 145                                          FTSDMC021_TP2_INI_REFT(8) |    \
 146                                          FTSDMC021_TP2_REF_INTV(0x180))
 147
 148 /*
 149  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 150  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 151  * C language.
 152  */
 153 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 154                                          FTSDMC021_CR1_DSZ(3)    |      \
 155                                          FTSDMC021_CR1_MBW(2)    |      \
 156                                          FTSDMC021_CR1_BNKSIZE(6))
 157
 158 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 159                                          FTSDMC021_CR2_IREF      |      \
 160                                          FTSDMC021_CR2_ISMR)
 161
 162 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 163 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 164                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 165
 166 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 167         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 168 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 169                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 170 #endif
 171
 172 /*
 173  * Physical Memory Map
 174  */
 175 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 176 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 177 #else
 178 #ifdef CONFIG_MEM_REMAP
 179 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 180 #else
 181 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 182 #endif
 183 #endif
 184
 185 #define PHYS_SDRAM_1 \
 186         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 187
 188 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 189 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 190 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 191 #else
 192 #ifdef CONFIG_MEM_REMAP
 193 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 194 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 195 #else
 196 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 197 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 198 #endif
 199 #endif
 200
 201 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 202
 203 #ifdef CONFIG_MEM_REMAP
 204 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 205                                         GENERATED_GBL_DATA_SIZE)
 206 #else
 207 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 208                                         GENERATED_GBL_DATA_SIZE)
 209 #endif /* CONFIG_MEM_REMAP */
 210
 211 /*
 212  * Static memory controller configuration
 213  */
 214 #define CONFIG_FTSMC020
 215
 216 #ifdef CONFIG_FTSMC020
 217 #include <faraday/ftsmc020.h>
 218
 219 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 220         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 221         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 222 }
 223
 224 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 225 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 226                                          FTSMC020_BANK_SIZE_32M |       \
 227                                          FTSMC020_BANK_MBW_32)
 228
 229 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 230                                          FTSMC020_TPR_AST(1)    |       \
 231                                          FTSMC020_TPR_CTW(1)    |       \
 232                                          FTSMC020_TPR_ATI(1)    |       \
 233                                          FTSMC020_TPR_AT2(1)    |       \
 234                                          FTSMC020_TPR_WTC(1)    |       \
 235                                          FTSMC020_TPR_AHT(1)    |       \
 236                                          FTSMC020_TPR_TRNA(1))
 237 #endif
 238
 239 /*
 240  * FLASH on ADP_AG101P is connected to BANK0
 241  * Just disalbe the other BANK to avoid detection error.
 242  */
 243 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 244                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 245                                  FTSMC020_BANK_SIZE_32M           |     \
 246                                  FTSMC020_BANK_MBW_32)
 247
 248 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 249                                  FTSMC020_TPR_CTW(3)   |        \
 250                                  FTSMC020_TPR_ATI(0xf) |        \
 251                                  FTSMC020_TPR_AT2(3)   |        \
 252                                  FTSMC020_TPR_WTC(3)   |        \
 253                                  FTSMC020_TPR_AHT(3)   |        \
 254                                  FTSMC020_TPR_TRNA(0xf))
 255
 256 #define FTSMC020_BANK1_CONFIG   (0x00)
 257 #define FTSMC020_BANK1_TIMING   (0x00)
 258 #endif /* CONFIG_FTSMC020 */
 259
 260 /*
 261  * FLASH and environment organization
 262  */
 263 /* use CFI framework */
 264
 265 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 266 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 267
 268 /* support JEDEC */
 269
 270 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 271 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 272 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 273 #else
 274 #ifdef CONFIG_MEM_REMAP
 275 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 276 #else
 277 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 278 #endif
 279 #endif  /* CONFIG_MEM_REMAP */
 280
 281 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 282 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 283 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 284
 285 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 286 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 287
 288 /* max number of memory banks */
 289 /*
 290  * There are 4 banks supported for this Controller,
 291  * but we have only 1 bank connected to flash on board
 292  */
 293 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 294 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 295 #endif
 296 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 297
 298 /* max number of sectors on one chip */
 299 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 300 #define CONFIG_SYS_MAX_FLASH_SECT       512
 301
 302 /* environments */
 303
 304 /*
 305  * For booting Linux, the board info and command line data
 306  * have to be in the first 16 MB of memory, since this is
 307  * the maximum mapped by the Linux kernel during initialization.
 308  */
 309
 310 /* Initial Memory map for Linux*/
 311 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 312 /* Increase max gunzip size */
 313 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 314
 315 #endif  /* __CONFIG_H */