include/configs/adp-ag101p.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ag101/ag101.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_BOOTP_SERVERIP
  19
  20 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  21 #define CONFIG_MEM_REMAP
  22 #endif
  23
  24 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  25 #ifdef CONFIG_OF_CONTROL
  26 #undef CONFIG_OF_SEPARATE
  27 #endif
  28 #endif
  29
  30 /*
  31  * Timer
  32  */
  33 #define VERSION_CLOCK           get_board_sys_clk()
  34
  35 /*
  36  * Use Externel CLOCK or PCLK
  37  */
  38 #undef CONFIG_FTRTC010_EXTCLK
  39
  40 #ifndef CONFIG_FTRTC010_EXTCLK
  41 #define CONFIG_FTRTC010_PCLK
  42 #endif
  43
  44 #ifdef CONFIG_FTRTC010_EXTCLK
  45 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  46 #else
  47 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  48 #endif
  49
  50 #define TIMER_LOAD_VAL  0xffffffff
  51
  52 /*
  53  * Real Time Clock
  54  */
  55 #define CONFIG_RTC_FTRTC010
  56
  57 /*
  58  * Real Time Clock Divider
  59  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  60  */
  61 #define OSC_5MHZ                        (5*1000000)
  62 #define OSC_CLK                         (4*OSC_5MHZ)
  63 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  64
  65 /*
  66  * Serial console configuration
  67  */
  68
  69 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  70 #define CONFIG_SYS_NS16550_SERIAL
  71 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  72 #ifndef CONFIG_DM_SERIAL
  73 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  74 #endif
  75 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  76
  77 /*
  78  * Miscellaneous configurable options
  79  */
  80
  81 /*
  82  * AHB Controller configuration
  83  */
  84 #define CONFIG_FTAHBC020S
  85
  86 #ifdef CONFIG_FTAHBC020S
  87 #include <faraday/ftahbc020s.h>
  88
  89 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  90 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
  91
  92 /*
  93  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  94  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  95  * in C language.
  96  */
  97 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  98         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  99                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
 100 #endif
 101
 102 /*
 103  * Watchdog
 104  */
 105 #define CONFIG_FTWDT010_WATCHDOG
 106
 107 /*
 108  * PMU Power controller configuration
 109  */
 110 #define CONFIG_PMU
 111 #define CONFIG_FTPMU010_POWER
 112
 113 #ifdef CONFIG_FTPMU010_POWER
 114 #include <faraday/ftpmu010.h>
 115 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 116 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 117                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 118                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 119                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 120                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 121                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 122                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 123 #endif
 124
 125 /*
 126  * SDRAM controller configuration
 127  */
 128 #define CONFIG_FTSDMC021
 129
 130 #ifdef CONFIG_FTSDMC021
 131 #include <faraday/ftsdmc021.h>
 132
 133 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 134                                          FTSDMC021_TP1_TRP(1)   |       \
 135                                          FTSDMC021_TP1_TRCD(1)  |       \
 136                                          FTSDMC021_TP1_TRF(3)   |       \
 137                                          FTSDMC021_TP1_TWR(1)   |       \
 138                                          FTSDMC021_TP1_TCL(2))
 139
 140 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 141                                          FTSDMC021_TP2_INI_REFT(8) |    \
 142                                          FTSDMC021_TP2_REF_INTV(0x180))
 143
 144 /*
 145  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 146  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 147  * C language.
 148  */
 149 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 150                                          FTSDMC021_CR1_DSZ(3)    |      \
 151                                          FTSDMC021_CR1_MBW(2)    |      \
 152                                          FTSDMC021_CR1_BNKSIZE(6))
 153
 154 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 155                                          FTSDMC021_CR2_IREF      |      \
 156                                          FTSDMC021_CR2_ISMR)
 157
 158 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 159 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 160                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 161
 162 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 163         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 164 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 165                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 166 #endif
 167
 168 /*
 169  * Physical Memory Map
 170  */
 171 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 172 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 173 #else
 174 #ifdef CONFIG_MEM_REMAP
 175 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 176 #else
 177 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 178 #endif
 179 #endif
 180
 181 #define PHYS_SDRAM_1 \
 182         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 183
 184 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 185 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 186 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 187 #else
 188 #ifdef CONFIG_MEM_REMAP
 189 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 190 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 191 #else
 192 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 193 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 194 #endif
 195 #endif
 196
 197 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 198
 199 #ifdef CONFIG_MEM_REMAP
 200 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 201                                         GENERATED_GBL_DATA_SIZE)
 202 #else
 203 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 204                                         GENERATED_GBL_DATA_SIZE)
 205 #endif /* CONFIG_MEM_REMAP */
 206
 207 /*
 208  * Static memory controller configuration
 209  */
 210 #define CONFIG_FTSMC020
 211
 212 #ifdef CONFIG_FTSMC020
 213 #include <faraday/ftsmc020.h>
 214
 215 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 216         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 217         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 218 }
 219
 220 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 221 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 222                                          FTSMC020_BANK_SIZE_32M |       \
 223                                          FTSMC020_BANK_MBW_32)
 224
 225 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 226                                          FTSMC020_TPR_AST(1)    |       \
 227                                          FTSMC020_TPR_CTW(1)    |       \
 228                                          FTSMC020_TPR_ATI(1)    |       \
 229                                          FTSMC020_TPR_AT2(1)    |       \
 230                                          FTSMC020_TPR_WTC(1)    |       \
 231                                          FTSMC020_TPR_AHT(1)    |       \
 232                                          FTSMC020_TPR_TRNA(1))
 233 #endif
 234
 235 /*
 236  * FLASH on ADP_AG101P is connected to BANK0
 237  * Just disalbe the other BANK to avoid detection error.
 238  */
 239 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 240                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 241                                  FTSMC020_BANK_SIZE_32M           |     \
 242                                  FTSMC020_BANK_MBW_32)
 243
 244 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 245                                  FTSMC020_TPR_CTW(3)   |        \
 246                                  FTSMC020_TPR_ATI(0xf) |        \
 247                                  FTSMC020_TPR_AT2(3)   |        \
 248                                  FTSMC020_TPR_WTC(3)   |        \
 249                                  FTSMC020_TPR_AHT(3)   |        \
 250                                  FTSMC020_TPR_TRNA(0xf))
 251
 252 #define FTSMC020_BANK1_CONFIG   (0x00)
 253 #define FTSMC020_BANK1_TIMING   (0x00)
 254 #endif /* CONFIG_FTSMC020 */
 255
 256 /*
 257  * FLASH and environment organization
 258  */
 259 /* use CFI framework */
 260
 261 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 262 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 263
 264 /* support JEDEC */
 265
 266 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 267 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 268 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 269 #else
 270 #ifdef CONFIG_MEM_REMAP
 271 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 272 #else
 273 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 274 #endif
 275 #endif  /* CONFIG_MEM_REMAP */
 276
 277 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 278 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 279 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 280
 281 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 282 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 283
 284 /* max number of memory banks */
 285 /*
 286  * There are 4 banks supported for this Controller,
 287  * but we have only 1 bank connected to flash on board
 288  */
 289 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 290 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 291 #endif
 292 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 293
 294 /* max number of sectors on one chip */
 295 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 296 #define CONFIG_SYS_MAX_FLASH_SECT       512
 297
 298 /* environments */
 299
 300 /*
 301  * For booting Linux, the board info and command line data
 302  * have to be in the first 16 MB of memory, since this is
 303  * the maximum mapped by the Linux kernel during initialization.
 304  */
 305
 306 /* Initial Memory map for Linux*/
 307 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 308 /* Increase max gunzip size */
 309 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 310
 311 #endif  /* __CONFIG_H */