include/configs/adp-ag101p.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ag101/ag101.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  19 #define CONFIG_MEM_REMAP
  20 #endif
  21
  22 /*
  23  * Timer
  24  */
  25 #define VERSION_CLOCK           get_board_sys_clk()
  26
  27 /*
  28  * Use Externel CLOCK or PCLK
  29  */
  30 #undef CONFIG_FTRTC010_EXTCLK
  31
  32 #ifndef CONFIG_FTRTC010_EXTCLK
  33 #define CONFIG_FTRTC010_PCLK
  34 #endif
  35
  36 #ifdef CONFIG_FTRTC010_EXTCLK
  37 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  38 #else
  39 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  40 #endif
  41
  42 #define TIMER_LOAD_VAL  0xffffffff
  43
  44 /*
  45  * Real Time Clock
  46  */
  47 #define CONFIG_RTC_FTRTC010
  48
  49 /*
  50  * Real Time Clock Divider
  51  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  52  */
  53 #define OSC_5MHZ                        (5*1000000)
  54 #define OSC_CLK                         (4*OSC_5MHZ)
  55 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  56
  57 /*
  58  * Serial console configuration
  59  */
  60
  61 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  62 #define CONFIG_SYS_NS16550_SERIAL
  63 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  64 #ifndef CONFIG_DM_SERIAL
  65 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  66 #endif
  67 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  68
  69 /*
  70  * Miscellaneous configurable options
  71  */
  72
  73 /*
  74  * AHB Controller configuration
  75  */
  76 #define CONFIG_FTAHBC020S
  77
  78 #ifdef CONFIG_FTAHBC020S
  79 #include <faraday/ftahbc020s.h>
  80
  81 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  82 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE    0x100
  83
  84 /*
  85  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  86  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  87  * in C language.
  88  */
  89 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  90         (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  91                                         FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  92 #endif
  93
  94 /*
  95  * Watchdog
  96  */
  97 #define CONFIG_FTWDT010_WATCHDOG
  98
  99 /*
 100  * PMU Power controller configuration
 101  */
 102 #define CONFIG_PMU
 103 #define CONFIG_FTPMU010_POWER
 104
 105 #ifdef CONFIG_FTPMU010_POWER
 106 #include <faraday/ftpmu010.h>
 107 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS          0x0E
 108 #define CONFIG_SYS_FTPMU010_SDRAMHTC    (FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
 109                                          FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
 110                                          FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
 111                                          FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
 112                                          FTPMU010_SDRAMHTC_CKE_DCSR      | \
 113                                          FTPMU010_SDRAMHTC_DQM_DCSR      | \
 114                                          FTPMU010_SDRAMHTC_SDCLK_DCSR)
 115 #endif
 116
 117 /*
 118  * SDRAM controller configuration
 119  */
 120 #define CONFIG_FTSDMC021
 121
 122 #ifdef CONFIG_FTSDMC021
 123 #include <faraday/ftsdmc021.h>
 124
 125 #define CONFIG_SYS_FTSDMC021_TP1        (FTSDMC021_TP1_TRAS(2)  |       \
 126                                          FTSDMC021_TP1_TRP(1)   |       \
 127                                          FTSDMC021_TP1_TRCD(1)  |       \
 128                                          FTSDMC021_TP1_TRF(3)   |       \
 129                                          FTSDMC021_TP1_TWR(1)   |       \
 130                                          FTSDMC021_TP1_TCL(2))
 131
 132 #define CONFIG_SYS_FTSDMC021_TP2        (FTSDMC021_TP2_INI_PREC(4) |    \
 133                                          FTSDMC021_TP2_INI_REFT(8) |    \
 134                                          FTSDMC021_TP2_REF_INTV(0x180))
 135
 136 /*
 137  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
 138  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
 139  * C language.
 140  */
 141 #define CONFIG_SYS_FTSDMC021_CR1        (FTSDMC021_CR1_DDW(2)    |      \
 142                                          FTSDMC021_CR1_DSZ(3)    |      \
 143                                          FTSDMC021_CR1_MBW(2)    |      \
 144                                          FTSDMC021_CR1_BNKSIZE(6))
 145
 146 #define CONFIG_SYS_FTSDMC021_CR2        (FTSDMC021_CR2_IPREC     |      \
 147                                          FTSDMC021_CR2_IREF      |      \
 148                                          FTSDMC021_CR2_ISMR)
 149
 150 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
 151 #define CONFIG_SYS_FTSDMC021_BANK0_BSR  (FTSDMC021_BANK_ENABLE   |      \
 152                                          CONFIG_SYS_FTSDMC021_BANK0_BASE)
 153
 154 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
 155         (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
 156 #define CONFIG_SYS_FTSDMC021_BANK1_BSR  (FTSDMC021_BANK_ENABLE   |      \
 157                                          CONFIG_SYS_FTSDMC021_BANK1_BASE)
 158 #endif
 159
 160 /*
 161  * Physical Memory Map
 162  */
 163 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 164 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 165 #else
 166 #ifdef CONFIG_MEM_REMAP
 167 #define PHYS_SDRAM_0    0x00000000      /* SDRAM Bank #1 */
 168 #else
 169 #define PHYS_SDRAM_0    0x80000000      /* SDRAM Bank #1 */
 170 #endif
 171 #endif
 172
 173 #define PHYS_SDRAM_1 \
 174         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 175
 176 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 177 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 178 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 179 #else
 180 #ifdef CONFIG_MEM_REMAP
 181 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 182 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 183 #else
 184 #define PHYS_SDRAM_0_SIZE       0x08000000      /* 128 MB */
 185 #define PHYS_SDRAM_1_SIZE       0x08000000      /* 128 MB */
 186 #endif
 187 #endif
 188
 189 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 190
 191 #ifdef CONFIG_MEM_REMAP
 192 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 193                                         GENERATED_GBL_DATA_SIZE)
 194 #else
 195 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 196                                         GENERATED_GBL_DATA_SIZE)
 197 #endif /* CONFIG_MEM_REMAP */
 198
 199 /*
 200  * Static memory controller configuration
 201  */
 202 #define CONFIG_FTSMC020
 203
 204 #ifdef CONFIG_FTSMC020
 205 #include <faraday/ftsmc020.h>
 206
 207 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 208         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 209         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 210 }
 211
 212 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 213 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 214                                          FTSMC020_BANK_SIZE_32M |       \
 215                                          FTSMC020_BANK_MBW_32)
 216
 217 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 218                                          FTSMC020_TPR_AST(1)    |       \
 219                                          FTSMC020_TPR_CTW(1)    |       \
 220                                          FTSMC020_TPR_ATI(1)    |       \
 221                                          FTSMC020_TPR_AT2(1)    |       \
 222                                          FTSMC020_TPR_WTC(1)    |       \
 223                                          FTSMC020_TPR_AHT(1)    |       \
 224                                          FTSMC020_TPR_TRNA(1))
 225 #endif
 226
 227 /*
 228  * FLASH on ADP_AG101P is connected to BANK0
 229  * Just disalbe the other BANK to avoid detection error.
 230  */
 231 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 232                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 233                                  FTSMC020_BANK_SIZE_32M           |     \
 234                                  FTSMC020_BANK_MBW_32)
 235
 236 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 237                                  FTSMC020_TPR_CTW(3)   |        \
 238                                  FTSMC020_TPR_ATI(0xf) |        \
 239                                  FTSMC020_TPR_AT2(3)   |        \
 240                                  FTSMC020_TPR_WTC(3)   |        \
 241                                  FTSMC020_TPR_AHT(3)   |        \
 242                                  FTSMC020_TPR_TRNA(0xf))
 243
 244 #define FTSMC020_BANK1_CONFIG   (0x00)
 245 #define FTSMC020_BANK1_TIMING   (0x00)
 246 #endif /* CONFIG_FTSMC020 */
 247
 248 /*
 249  * FLASH and environment organization
 250  */
 251 /* use CFI framework */
 252
 253 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 254 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 255
 256 /* support JEDEC */
 257
 258 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 259 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 260 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 261 #else
 262 #ifdef CONFIG_MEM_REMAP
 263 #define PHYS_FLASH_1                    0x80000000      /* BANK 0 */
 264 #else
 265 #define PHYS_FLASH_1                    0x00000000      /* BANK 0 */
 266 #endif
 267 #endif  /* CONFIG_MEM_REMAP */
 268
 269 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 270 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 271
 272 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 273 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 274
 275 /* max number of memory banks */
 276 /*
 277  * There are 4 banks supported for this Controller,
 278  * but we have only 1 bank connected to flash on board
 279  */
 280 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 281
 282 /* max number of sectors on one chip */
 283 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 284 #define CONFIG_SYS_MAX_FLASH_SECT       512
 285
 286 /* environments */
 287
 288 /*
 289  * For booting Linux, the board info and command line data
 290  * have to be in the first 16 MB of memory, since this is
 291  * the maximum mapped by the Linux kernel during initialization.
 292  */
 293
 294 /* Initial Memory map for Linux*/
 295 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 296 /* Increase max gunzip size */
 297 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 298
 299 #endif  /* __CONFIG_H */