include/configs/adp-ae3xx.h

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   4  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #include <asm/arch-ae3xx/ae3xx.h>
  13
  14 /*
  15  * CPU and Board Configuration Options
  16  */
  17 #define CONFIG_USE_INTERRUPT
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  22
  23 #define CONFIG_CMDLINE_EDITING
  24
  25 #define CONFIG_ARCH_MAP_SYSMEM
  26
  27 #define CONFIG_BOOTP_SEND_HOSTNAME
  28 #define CONFIG_BOOTP_SERVERIP
  29
  30 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  31 #define CONFIG_SYS_TEXT_BASE    0x00500000
  32 #ifdef CONFIG_OF_CONTROL
  33 #undef CONFIG_OF_SEPARATE
  34 #define CONFIG_OF_EMBED
  35 #endif
  36 #else
  37
  38 #define CONFIG_SYS_TEXT_BASE    0x80000000
  39 #endif
  40
  41 /*
  42  * Timer
  43  */
  44 #define CONFIG_SYS_CLK_FREQ     39062500
  45 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  46
  47 /*
  48  * Use Externel CLOCK or PCLK
  49  */
  50 #undef CONFIG_FTRTC010_EXTCLK
  51
  52 #ifndef CONFIG_FTRTC010_EXTCLK
  53 #define CONFIG_FTRTC010_PCLK
  54 #endif
  55
  56 #ifdef CONFIG_FTRTC010_EXTCLK
  57 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  58 #else
  59 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  60 #endif
  61
  62 #define TIMER_LOAD_VAL  0xffffffff
  63
  64 /*
  65  * Real Time Clock
  66  */
  67 #define CONFIG_RTC_FTRTC010
  68
  69 /*
  70  * Real Time Clock Divider
  71  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  72  */
  73 #define OSC_5MHZ                        (5*1000000)
  74 #define OSC_CLK                         (4*OSC_5MHZ)
  75 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  76
  77 /*
  78  * Serial console configuration
  79  */
  80
  81 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  82 #define CONFIG_CONS_INDEX               1
  83 #define CONFIG_SYS_NS16550_SERIAL
  84 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  85 #ifndef CONFIG_DM_SERIAL
  86 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  87 #endif
  88 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  89
  90 /*
  91  * SD (MMC) controller
  92  */
  93 #define CONFIG_FTSDC010_NUMBER          1
  94 #define CONFIG_FTSDC010_SDIO
  95
  96 /*
  97  * Miscellaneous configurable options
  98  */
  99 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 100
 101 /*
 102  * Size of malloc() pool
 103  */
 104 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
 105 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 106
 107 /*
 108  * Physical Memory Map
 109  */
 110 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
 111
 112 #define PHYS_SDRAM_1 \
 113         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
 114
 115 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 bank of DRAM */
 116
 117 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
 118 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
 119
 120 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 121
 122 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 123                                         GENERATED_GBL_DATA_SIZE)
 124
 125 /*
 126  * Load address and memory test area should agree with
 127  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 128  */
 129 #define CONFIG_SYS_LOAD_ADDR            0x300000
 130
 131 /* memtest works on 63 MB in DRAM */
 132 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_0
 133 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_0 + 0x03F00000)
 134
 135 /*
 136  * Static memory controller configuration
 137  */
 138 #define CONFIG_FTSMC020
 139
 140 #ifdef CONFIG_FTSMC020
 141 #include <faraday/ftsmc020.h>
 142
 143 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 144         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 145         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 146 }
 147
 148 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 149 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 150                                          FTSMC020_BANK_SIZE_32M |       \
 151                                          FTSMC020_BANK_MBW_32)
 152
 153 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 154                                          FTSMC020_TPR_AST(1)    |       \
 155                                          FTSMC020_TPR_CTW(1)    |       \
 156                                          FTSMC020_TPR_ATI(1)    |       \
 157                                          FTSMC020_TPR_AT2(1)    |       \
 158                                          FTSMC020_TPR_WTC(1)    |       \
 159                                          FTSMC020_TPR_AHT(1)    |       \
 160                                          FTSMC020_TPR_TRNA(1))
 161 #endif
 162
 163 /*
 164  * FLASH on ADP_AG101P is connected to BANK0
 165  * Just disalbe the other BANK to avoid detection error.
 166  */
 167 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 168                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 169                                  FTSMC020_BANK_SIZE_32M           |     \
 170                                  FTSMC020_BANK_MBW_32)
 171
 172 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 173                                  FTSMC020_TPR_CTW(3)   |        \
 174                                  FTSMC020_TPR_ATI(0xf) |        \
 175                                  FTSMC020_TPR_AT2(3)   |        \
 176                                  FTSMC020_TPR_WTC(3)   |        \
 177                                  FTSMC020_TPR_AHT(3)   |        \
 178                                  FTSMC020_TPR_TRNA(0xf))
 179
 180 #define FTSMC020_BANK1_CONFIG   (0x00)
 181 #define FTSMC020_BANK1_TIMING   (0x00)
 182 #endif /* CONFIG_FTSMC020 */
 183
 184 /*
 185  * FLASH and environment organization
 186  */
 187 /* use CFI framework */
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_FLASH_CFI_DRIVER
 190
 191 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 192 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 193 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 194
 195 /* support JEDEC */
 196 #ifdef CONFIG_CFI_FLASH
 197 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 198 #endif
 199
 200 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 201 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 202 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 203 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 204 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 205
 206 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 207 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 208
 209 /* max number of memory banks */
 210 /*
 211  * There are 4 banks supported for this Controller,
 212  * but we have only 1 bank connected to flash on board
 213  */
 214 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 216 #endif
 217 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 218
 219 /* max number of sectors on one chip */
 220 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 221 #define CONFIG_SYS_MAX_FLASH_SECT       512
 222
 223 /* environments */
 224 #define CONFIG_ENV_SPI_BUS              0
 225 #define CONFIG_ENV_SPI_CS               0
 226 #define CONFIG_ENV_SPI_MAX_HZ           50000000
 227 #define CONFIG_ENV_SPI_MODE             0
 228 #define CONFIG_ENV_SECT_SIZE            0x1000
 229 #define CONFIG_ENV_OFFSET               0x140000
 230 #define CONFIG_ENV_SIZE                 8192
 231 #define CONFIG_ENV_OVERWRITE
 232
 233
 234 /* SPI FLASH */
 235 #define CONFIG_SF_DEFAULT_BUS           0
 236 #define CONFIG_SF_DEFAULT_CS            0
 237 #define CONFIG_SF_DEFAULT_SPEED         1000000
 238 #define CONFIG_SF_DEFAULT_MODE          0
 239
 240 /*
 241  * For booting Linux, the board info and command line data
 242  * have to be in the first 16 MB of memory, since this is
 243  * the maximum mapped by the Linux kernel during initialization.
 244  */
 245
 246 /* Initial Memory map for Linux*/
 247 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 248 /* Increase max gunzip size */
 249 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 250
 251 #endif  /* __CONFIG_H */