include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  19
  20 /*
  21  * Timer
  22  */
  23 #define VERSION_CLOCK           get_board_sys_clk()
  24
  25 /*
  26  * Use Externel CLOCK or PCLK
  27  */
  28 #undef CONFIG_FTRTC010_EXTCLK
  29
  30 #ifndef CONFIG_FTRTC010_EXTCLK
  31 #define CONFIG_FTRTC010_PCLK
  32 #endif
  33
  34 #ifdef CONFIG_FTRTC010_EXTCLK
  35 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  36 #else
  37 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  38 #endif
  39
  40 #define TIMER_LOAD_VAL  0xffffffff
  41
  42 /*
  43  * Real Time Clock
  44  */
  45 #define CONFIG_RTC_FTRTC010
  46
  47 /*
  48  * Real Time Clock Divider
  49  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  50  */
  51 #define OSC_5MHZ                        (5*1000000)
  52 #define OSC_CLK                         (4*OSC_5MHZ)
  53 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  54
  55 /*
  56  * Serial console configuration
  57  */
  58
  59 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  60 #define CONFIG_SYS_NS16550_SERIAL
  61 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  62 #ifndef CONFIG_DM_SERIAL
  63 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  64 #endif
  65 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  66
  67 /*
  68  * Miscellaneous configurable options
  69  */
  70
  71 /*
  72  * Size of malloc() pool
  73  */
  74 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  75
  76 /*
  77  * Physical Memory Map
  78  */
  79 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  80
  81 #define PHYS_SDRAM_1 \
  82         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  83
  84 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
  85 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
  86
  87 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
  88
  89 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  90                                         GENERATED_GBL_DATA_SIZE)
  91
  92 /*
  93  * Static memory controller configuration
  94  */
  95 #define CONFIG_FTSMC020
  96
  97 #ifdef CONFIG_FTSMC020
  98 #include <faraday/ftsmc020.h>
  99
 100 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 101         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 102         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 103 }
 104
 105 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 106 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 107                                          FTSMC020_BANK_SIZE_32M |       \
 108                                          FTSMC020_BANK_MBW_32)
 109
 110 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 111                                          FTSMC020_TPR_AST(1)    |       \
 112                                          FTSMC020_TPR_CTW(1)    |       \
 113                                          FTSMC020_TPR_ATI(1)    |       \
 114                                          FTSMC020_TPR_AT2(1)    |       \
 115                                          FTSMC020_TPR_WTC(1)    |       \
 116                                          FTSMC020_TPR_AHT(1)    |       \
 117                                          FTSMC020_TPR_TRNA(1))
 118 #endif
 119
 120 /*
 121  * FLASH on ADP_AG101P is connected to BANK0
 122  * Just disalbe the other BANK to avoid detection error.
 123  */
 124 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 125                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 126                                  FTSMC020_BANK_SIZE_32M           |     \
 127                                  FTSMC020_BANK_MBW_32)
 128
 129 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 130                                  FTSMC020_TPR_CTW(3)   |        \
 131                                  FTSMC020_TPR_ATI(0xf) |        \
 132                                  FTSMC020_TPR_AT2(3)   |        \
 133                                  FTSMC020_TPR_WTC(3)   |        \
 134                                  FTSMC020_TPR_AHT(3)   |        \
 135                                  FTSMC020_TPR_TRNA(0xf))
 136
 137 #define FTSMC020_BANK1_CONFIG   (0x00)
 138 #define FTSMC020_BANK1_TIMING   (0x00)
 139 #endif /* CONFIG_FTSMC020 */
 140
 141 /*
 142  * FLASH and environment organization
 143  */
 144 /* use CFI framework */
 145
 146 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 147 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 148
 149 /* support JEDEC */
 150
 151 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 152 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 153 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 154 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 155
 156 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 157 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 158
 159 /* max number of memory banks */
 160 /*
 161  * There are 4 banks supported for this Controller,
 162  * but we have only 1 bank connected to flash on board
 163  */
 164 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 165
 166 /* max number of sectors on one chip */
 167 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 168 #define CONFIG_SYS_MAX_FLASH_SECT       512
 169
 170 /* environments */
 171
 172
 173 /* SPI FLASH */
 174
 175 /*
 176  * For booting Linux, the board info and command line data
 177  * have to be in the first 16 MB of memory, since this is
 178  * the maximum mapped by the Linux kernel during initialization.
 179  */
 180
 181 /* Initial Memory map for Linux*/
 182 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 183 /* Increase max gunzip size */
 184 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 185
 186 #endif  /* __CONFIG_H */