include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  19
  20 #define CONFIG_ARCH_MAP_SYSMEM
  21
  22 #define CONFIG_BOOTP_SERVERIP
  23
  24 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  25 #ifdef CONFIG_OF_CONTROL
  26 #undef CONFIG_OF_SEPARATE
  27 #define CONFIG_OF_EMBED
  28 #endif
  29 #endif
  30
  31 /*
  32  * Timer
  33  */
  34 #define CONFIG_SYS_CLK_FREQ     39062500
  35 #define VERSION_CLOCK           CONFIG_SYS_CLK_FREQ
  36
  37 /*
  38  * Use Externel CLOCK or PCLK
  39  */
  40 #undef CONFIG_FTRTC010_EXTCLK
  41
  42 #ifndef CONFIG_FTRTC010_EXTCLK
  43 #define CONFIG_FTRTC010_PCLK
  44 #endif
  45
  46 #ifdef CONFIG_FTRTC010_EXTCLK
  47 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  48 #else
  49 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  50 #endif
  51
  52 #define TIMER_LOAD_VAL  0xffffffff
  53
  54 /*
  55  * Real Time Clock
  56  */
  57 #define CONFIG_RTC_FTRTC010
  58
  59 /*
  60  * Real Time Clock Divider
  61  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  62  */
  63 #define OSC_5MHZ                        (5*1000000)
  64 #define OSC_CLK                         (4*OSC_5MHZ)
  65 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  66
  67 /*
  68  * Serial console configuration
  69  */
  70
  71 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  72 #define CONFIG_SYS_NS16550_SERIAL
  73 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  74 #ifndef CONFIG_DM_SERIAL
  75 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  76 #endif
  77 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  78
  79 /*
  80  * Miscellaneous configurable options
  81  */
  82
  83 /*
  84  * Size of malloc() pool
  85  */
  86 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  87 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
  88
  89 /*
  90  * Physical Memory Map
  91  */
  92 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  93
  94 #define PHYS_SDRAM_1 \
  95         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  96
  97 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
  98 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
  99
 100 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
 101
 102 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
 103                                         GENERATED_GBL_DATA_SIZE)
 104
 105 /*
 106  * Static memory controller configuration
 107  */
 108 #define CONFIG_FTSMC020
 109
 110 #ifdef CONFIG_FTSMC020
 111 #include <faraday/ftsmc020.h>
 112
 113 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 114         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 115         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 116 }
 117
 118 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 119 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 120                                          FTSMC020_BANK_SIZE_32M |       \
 121                                          FTSMC020_BANK_MBW_32)
 122
 123 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 124                                          FTSMC020_TPR_AST(1)    |       \
 125                                          FTSMC020_TPR_CTW(1)    |       \
 126                                          FTSMC020_TPR_ATI(1)    |       \
 127                                          FTSMC020_TPR_AT2(1)    |       \
 128                                          FTSMC020_TPR_WTC(1)    |       \
 129                                          FTSMC020_TPR_AHT(1)    |       \
 130                                          FTSMC020_TPR_TRNA(1))
 131 #endif
 132
 133 /*
 134  * FLASH on ADP_AG101P is connected to BANK0
 135  * Just disalbe the other BANK to avoid detection error.
 136  */
 137 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 138                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 139                                  FTSMC020_BANK_SIZE_32M           |     \
 140                                  FTSMC020_BANK_MBW_32)
 141
 142 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 143                                  FTSMC020_TPR_CTW(3)   |        \
 144                                  FTSMC020_TPR_ATI(0xf) |        \
 145                                  FTSMC020_TPR_AT2(3)   |        \
 146                                  FTSMC020_TPR_WTC(3)   |        \
 147                                  FTSMC020_TPR_AHT(3)   |        \
 148                                  FTSMC020_TPR_TRNA(0xf))
 149
 150 #define FTSMC020_BANK1_CONFIG   (0x00)
 151 #define FTSMC020_BANK1_TIMING   (0x00)
 152 #endif /* CONFIG_FTSMC020 */
 153
 154 /*
 155  * FLASH and environment organization
 156  */
 157 /* use CFI framework */
 158
 159 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 160 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 161
 162 /* support JEDEC */
 163 #ifdef CONFIG_CFI_FLASH
 164 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       1
 165 #endif
 166
 167 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 168 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 169 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 170 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 171 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 172
 173 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 174 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 175
 176 /* max number of memory banks */
 177 /*
 178  * There are 4 banks supported for this Controller,
 179  * but we have only 1 bank connected to flash on board
 180  */
 181 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 183 #endif
 184 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 185
 186 /* max number of sectors on one chip */
 187 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 188 #define CONFIG_SYS_MAX_FLASH_SECT       512
 189
 190 /* environments */
 191
 192
 193 /* SPI FLASH */
 194
 195 /*
 196  * For booting Linux, the board info and command line data
 197  * have to be in the first 16 MB of memory, since this is
 198  * the maximum mapped by the Linux kernel during initialization.
 199  */
 200
 201 /* Initial Memory map for Linux*/
 202 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 203 /* Increase max gunzip size */
 204 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 205
 206 #endif  /* __CONFIG_H */