include/configs/adp-ae3xx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Andes Technology Corporation
   4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
   5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <asm/arch-ae3xx/ae3xx.h>
  12
  13 /*
  14  * CPU and Board Configuration Options
  15  */
  16 #define CONFIG_USE_INTERRUPT
  17
  18 #define CONFIG_SKIP_TRUNOFF_WATCHDOG
  19
  20 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  21 #ifdef CONFIG_OF_CONTROL
  22 #undef CONFIG_OF_SEPARATE
  23 #endif
  24 #endif
  25
  26 /*
  27  * Timer
  28  */
  29 #define VERSION_CLOCK           get_board_sys_clk()
  30
  31 /*
  32  * Use Externel CLOCK or PCLK
  33  */
  34 #undef CONFIG_FTRTC010_EXTCLK
  35
  36 #ifndef CONFIG_FTRTC010_EXTCLK
  37 #define CONFIG_FTRTC010_PCLK
  38 #endif
  39
  40 #ifdef CONFIG_FTRTC010_EXTCLK
  41 #define TIMER_CLOCK     32768                   /* CONFIG_FTRTC010_EXTCLK */
  42 #else
  43 #define TIMER_CLOCK     CONFIG_SYS_HZ           /* CONFIG_FTRTC010_PCLK */
  44 #endif
  45
  46 #define TIMER_LOAD_VAL  0xffffffff
  47
  48 /*
  49  * Real Time Clock
  50  */
  51 #define CONFIG_RTC_FTRTC010
  52
  53 /*
  54  * Real Time Clock Divider
  55  * RTC_DIV_COUNT                        (OSC_CLK/OSC_5MHZ)
  56  */
  57 #define OSC_5MHZ                        (5*1000000)
  58 #define OSC_CLK                         (4*OSC_5MHZ)
  59 #define RTC_DIV_COUNT                   (0.5)   /* Why?? */
  60
  61 /*
  62  * Serial console configuration
  63  */
  64
  65 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  66 #define CONFIG_SYS_NS16550_SERIAL
  67 #define CONFIG_SYS_NS16550_COM1         CONFIG_FTUART010_02_BASE
  68 #ifndef CONFIG_DM_SERIAL
  69 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  70 #endif
  71 #define CONFIG_SYS_NS16550_CLK          ((18432000 * 20) / 25)  /* AG101P */
  72
  73 /*
  74  * Miscellaneous configurable options
  75  */
  76
  77 /*
  78  * Size of malloc() pool
  79  */
  80 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  81
  82 /*
  83  * Physical Memory Map
  84  */
  85 #define PHYS_SDRAM_0    0x00000000  /* SDRAM Bank #1 */
  86
  87 #define PHYS_SDRAM_1 \
  88         (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)      /* SDRAM Bank #2 */
  89
  90 #define PHYS_SDRAM_0_SIZE       0x20000000      /* 512 MB */
  91 #define PHYS_SDRAM_1_SIZE       0x20000000      /* 512 MB */
  92
  93 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_0
  94
  95 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  96                                         GENERATED_GBL_DATA_SIZE)
  97
  98 /*
  99  * Static memory controller configuration
 100  */
 101 #define CONFIG_FTSMC020
 102
 103 #ifdef CONFIG_FTSMC020
 104 #include <faraday/ftsmc020.h>
 105
 106 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 107         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 108         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 109 }
 110
 111 #ifndef CONFIG_SKIP_LOWLEVEL_INIT       /* FLASH is on BANK 0 */
 112 #define FTSMC020_BANK0_LOWLV_CONFIG     (FTSMC020_BANK_ENABLE   |       \
 113                                          FTSMC020_BANK_SIZE_32M |       \
 114                                          FTSMC020_BANK_MBW_32)
 115
 116 #define FTSMC020_BANK0_LOWLV_TIMING     (FTSMC020_TPR_RBE       |       \
 117                                          FTSMC020_TPR_AST(1)    |       \
 118                                          FTSMC020_TPR_CTW(1)    |       \
 119                                          FTSMC020_TPR_ATI(1)    |       \
 120                                          FTSMC020_TPR_AT2(1)    |       \
 121                                          FTSMC020_TPR_WTC(1)    |       \
 122                                          FTSMC020_TPR_AHT(1)    |       \
 123                                          FTSMC020_TPR_TRNA(1))
 124 #endif
 125
 126 /*
 127  * FLASH on ADP_AG101P is connected to BANK0
 128  * Just disalbe the other BANK to avoid detection error.
 129  */
 130 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 131                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 132                                  FTSMC020_BANK_SIZE_32M           |     \
 133                                  FTSMC020_BANK_MBW_32)
 134
 135 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_AST(3)   |        \
 136                                  FTSMC020_TPR_CTW(3)   |        \
 137                                  FTSMC020_TPR_ATI(0xf) |        \
 138                                  FTSMC020_TPR_AT2(3)   |        \
 139                                  FTSMC020_TPR_WTC(3)   |        \
 140                                  FTSMC020_TPR_AHT(3)   |        \
 141                                  FTSMC020_TPR_TRNA(0xf))
 142
 143 #define FTSMC020_BANK1_CONFIG   (0x00)
 144 #define FTSMC020_BANK1_TIMING   (0x00)
 145 #endif /* CONFIG_FTSMC020 */
 146
 147 /*
 148  * FLASH and environment organization
 149  */
 150 /* use CFI framework */
 151
 152 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 153 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
 154
 155 /* support JEDEC */
 156 #ifdef CONFIG_CFI_FLASH
 157 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT
 158 #endif
 159
 160 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
 161 #define PHYS_FLASH_1                    0x88000000      /* BANK 0 */
 162 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 163 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, }
 164 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 165
 166 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* TO for Flash Erase (ms) */
 167 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* TO for Flash Write (ms) */
 168
 169 /* max number of memory banks */
 170 /*
 171  * There are 4 banks supported for this Controller,
 172  * but we have only 1 bank connected to flash on board
 173  */
 174 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 175 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
 176
 177 /* max number of sectors on one chip */
 178 #define CONFIG_FLASH_SECTOR_SIZE        (0x10000*2)
 179 #define CONFIG_SYS_MAX_FLASH_SECT       512
 180
 181 /* environments */
 182
 183
 184 /* SPI FLASH */
 185
 186 /*
 187  * For booting Linux, the board info and command line data
 188  * have to be in the first 16 MB of memory, since this is
 189  * the maximum mapped by the Linux kernel during initialization.
 190  */
 191
 192 /* Initial Memory map for Linux*/
 193 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
 194 /* Increase max gunzip size */
 195 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
 196
 197 #endif  /* __CONFIG_H */