include/configs/a4m072.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is a MPC5200 CPU */
  20 #define CONFIG_A4M072           1       /* ... on A4M072 board */
  21 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  24
  25 #define CONFIG_MISC_INIT_R
  26
  27 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  28
  29 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  30
  31 /*
  32  * Serial console configuration
  33  */
  34 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  35 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  36 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  37 /* define to enable silent console */
  38 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  39
  40 /*
  41  * PCI Mapping:
  42  * 0x40000000 - 0x4fffffff - PCI Memory
  43  * 0x50000000 - 0x50ffffff - PCI IO Space
  44  */
  45
  46 #if defined(CONFIG_PCI)
  47 #define CONFIG_PCI_SCAN_SHOW    1
  48 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  49
  50 #define CONFIG_PCI_MEM_BUS      0x40000000
  51 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  52 #define CONFIG_PCI_MEM_SIZE     0x10000000
  53
  54 #define CONFIG_PCI_IO_BUS       0x50000000
  55 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  56 #define CONFIG_PCI_IO_SIZE      0x01000000
  57 #endif
  58
  59 #define CONFIG_SYS_XLB_PIPELINING       1
  60
  61 #undef CONFIG_EEPRO100
  62
  63 /* Partitions */
  64 #define CONFIG_DOS_PARTITION
  65
  66 /* USB */
  67 #define CONFIG_USB_OHCI_NEW
  68 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  69 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  70 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  71 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
  72 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
  73 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  74
  75 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  76
  77 /*
  78  * BOOTP options
  79  */
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_GATEWAY
  83 #define CONFIG_BOOTP_HOSTNAME
  84
  85 /*
  86  * Command line configuration.
  87  */
  88 #define CONFIG_CMD_EEPROM
  89 #define CONFIG_CMD_IDE
  90 #define CONFIG_CMD_DISPLAY
  91
  92 #if defined(CONFIG_PCI)
  93 #define CONFIG_CMD_PCI
  94 #endif
  95
  96 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low with 32 MB Flash */
  97 #define CONFIG_SYS_LOWBOOT              1
  98 #define CONFIG_SYS_LOWBOOT32            1
  99 #endif
 100
 101 /*
 102  * Autobooting
 103  */
 104
 105 #define CONFIG_SYS_AUTOLOAD     "n"
 106
 107 #undef  CONFIG_BOOTARGS
 108 #define CONFIG_PREBOOT                          "run try_update"
 109
 110 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 111         "bk=run add_mtd ; run add_consolespec ; bootm 200000\0"         \
 112         "cf1=diskboot 200000 0:1\0"                                     \
 113         "bootcmd_cf1=run bcf1\0"                                        \
 114         "bcf=setenv bootargs root=/dev/hda3\0"                          \
 115         "bootcmd_nfs=run bnfs\0"                                        \
 116         "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
 117                 "panic=1\0"                                             \
 118         "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"                \
 119                         "run norargs addip; run bk\0"                   \
 120         "bnfs=nfs 200000 ${rootpath}/boot/uImage;"                      \
 121                         "run nfsargs addip ; run bk\0"                  \
 122         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 123                                 "nfsroot=${serverip}:${rootpath}\0"     \
 124         "try_update=usb start;sleep 2;usb start;sleep 1;"               \
 125                         "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"   \
 126                         "source 2F0000\0"                               \
 127         "env_addr=FE060000\0"                                           \
 128         "kernel_addr=FE100000\0"                                        \
 129         "rootfs_addr=FE200000\0"                                        \
 130         "add_mtd=setenv bootargs ${bootargs} mtdparts="                 \
 131                 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"      \
 132         "bcf1=run cf1; run bcf; run addip; run bk\0"                    \
 133         "add_consolespec=setenv bootargs ${bootargs} "                  \
 134                                 "console=/dev/null quiet\0"             \
 135         "addip=if test -n ${ethaddr};"                                  \
 136                 "then if test -n ${ipaddr};"                            \
 137                         "then setenv bootargs ${bootargs} "             \
 138                                 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
 139                                 "${netmask}:${hostname}:${netdev}:off;" \
 140                         "fi;"                                           \
 141                 "else;"                                                 \
 142                         "setenv bootargs ${bootargs} no_ethaddr;"       \
 143                 "fi\0"                                                  \
 144         "hostname=CPUP0\0"                                              \
 145         "netdev=eth0\0"                                                 \
 146         "bootcmd=run bootcmd_nor\0"                                     \
 147         ""
 148 /*
 149  * IPB Bus clocking configuration.
 150  */
 151 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 152
 153 /*
 154  * I2C configuration
 155  */
 156 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 157 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 158
 159 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 160 #define CONFIG_SYS_I2C_SLAVE            0x7F
 161
 162 /*
 163  * EEPROM configuration
 164  */
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1010010x */
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 169 #define CONFIG_SYS_EEPROM_WREN                  1
 170 #define CONFIG_SYS_EEPROM_WP                    GPIO_PSC2_4
 171
 172 /*
 173  * Flash configuration
 174  */
 175 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 176 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 177 #if !defined(CONFIG_SYS_LOWBOOT)
 178 #error "CONFIG_SYS_LOWBOOT not defined?"
 179 #else   /* CONFIG_SYS_LOWBOOT */
 180 #if defined(CONFIG_SYS_LOWBOOT32)
 181 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 182 #endif
 183 #endif  /* CONFIG_SYS_LOWBOOT */
 184
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 186 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 187 #define CONFIG_FLASH_CFI_DRIVER
 188 #define CONFIG_SYS_FLASH_CFI
 189 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 190 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS0_START}
 191 #define CONFIG_SYS_FLASH_BANKS_SIZES    {CONFIG_SYS_CS0_SIZE}
 192
 193 /*
 194  * Environment settings
 195  */
 196 #define CONFIG_ENV_IS_IN_FLASH  1
 197 #define CONFIG_ENV_SIZE         0x10000
 198 #define CONFIG_ENV_SECT_SIZE    0x20000
 199 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 200 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 201
 202 #define CONFIG_ENV_OVERWRITE    1
 203
 204 /*
 205  * Memory map
 206  */
 207 #define CONFIG_SYS_MBAR         0xF0000000
 208 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 209 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 210
 211 /* Use SRAM until RAM will be available */
 212 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 213 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 214
 215 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 216 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 217
 218 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 220 #   define CONFIG_SYS_RAMBOOT           1
 221 #endif
 222
 223 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 224 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 225 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 226
 227 /*
 228  * Ethernet configuration
 229  */
 230 #define CONFIG_MPC5xxx_FEC      1
 231 #define CONFIG_MPC5xxx_FEC_MII100
 232 /*
 233  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 234  */
 235 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 236 #define CONFIG_PHY_ADDR         0x1f
 237 #define CONFIG_PHY_TYPE         0x79c874                /* AMD Phy Controller */
 238
 239 /*
 240  * GPIO configuration
 241  */
 242 #define CONFIG_SYS_GPS_PORT_CONFIG      0x18000004
 243
 244 /*
 245  * Miscellaneous configurable options
 246  */
 247 #define CONFIG_CMDLINE_EDITING  1
 248 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 249 #if defined(CONFIG_CMD_KGDB)
 250 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 251 #else
 252 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 253 #endif
 254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 255 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 256 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 257
 258 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 259 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 260
 261 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 262
 263 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 264 #if defined(CONFIG_CMD_KGDB)
 265 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 266 #endif
 267
 268 /*
 269  * Various low-level settings
 270  */
 271 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 272 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 273 /* Flash at CSBoot, CS0 */
 274 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 275 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 276 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 277 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 278 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 279 /* External SRAM at CS1 */
 280 #define CONFIG_SYS_CS1_START            0x62000000
 281 #define CONFIG_SYS_CS1_SIZE             0x00400000
 282 #define CONFIG_SYS_CS1_CFG              0x00009930
 283 #define CONFIG_SYS_SRAM_BASE            CONFIG_SYS_CS1_START
 284 #define CONFIG_SYS_SRAM_SIZE            CONFIG_SYS_CS1_SIZE
 285 /* LED display at CS7 */
 286 #define CONFIG_SYS_CS7_START            0x6a000000
 287 #define CONFIG_SYS_CS7_SIZE             (64*1024)
 288 #define CONFIG_SYS_CS7_CFG              0x0000bf30
 289
 290 #define CONFIG_SYS_CS_BURST             0x00000000
 291 #define CONFIG_SYS_CS_DEADCYCLE         0x33333003
 292
 293 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 294
 295 /*-----------------------------------------------------------------------
 296  * USB stuff
 297  *-----------------------------------------------------------------------
 298  */
 299 #define CONFIG_USB_CLOCK        0x0001BBBB
 300 #define CONFIG_USB_CONFIG       0x00001000 /* 0x4000 for SE mode */
 301
 302 /*-----------------------------------------------------------------------
 303  * IDE/ATA stuff Supports IDE harddisk
 304  *-----------------------------------------------------------------------
 305  */
 306
 307 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 308
 309 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 310 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 311
 312 #define CONFIG_IDE_PREINIT
 313
 314 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 315 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 316
 317 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 318
 319 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 320
 321 /* Offset for data I/O                  */
 322 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 323
 324 /* Offset for normal register accesses  */
 325 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 326
 327 /* Offset for alternate registers       */
 328 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 329
 330 /* Interval between registers                                                */
 331 #define CONFIG_SYS_ATA_STRIDE          4
 332
 333 #define CONFIG_ATAPI                   1
 334
 335 /*-----------------------------------------------------------------------
 336  * Open firmware flat tree support
 337  *-----------------------------------------------------------------------
 338  */
 339 #define OF_CPU                  "PowerPC,5200@0"
 340 #define OF_SOC                  "soc5200@f0000000"
 341 #define OF_TBCLK                (bd->bi_busfreq / 4)
 342 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 343
 344 /* Support for the 7-segment display */
 345 #define CONFIG_SYS_DISP_CHR_RAM      CONFIG_SYS_CS7_START
 346 #define CONFIG_SHOW_ACTIVITY            /* used for display realization */
 347
 348 #define CONFIG_SHOW_BOOT_PROGRESS
 349
 350 #endif /* __CONFIG_H */