Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / a3m071.h
1 /*
2  * Copyright 2012 Stefan Roese <sr@denx.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17
18 #ifndef __CONFIG_H
19 #define __CONFIG_H
20
21 /*
22  * High Level Configuration Options
23  * (easy to change)
24  */
25
26 #define CONFIG_MPC5200
27 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
28 #define CONFIG_A3M071                   /* ... on A3M071 board */
29
30 #define CONFIG_SYS_TEXT_BASE    0x01000000      /* boot low for 32 MiB boards */
31
32 #define CONFIG_SPL_TARGET       "u-boot-img.bin"
33
34 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
35
36 #define CONFIG_MISC_INIT_R
37 #define CONFIG_SYS_LOWBOOT              /* Enable lowboot       */
38
39 #ifdef CONFIG_A4M2K
40 #define CONFIG_HOSTNAME         a4m2k
41 #else
42 #define CONFIG_HOSTNAME         a3m071
43 #endif
44
45 /*
46  * Serial console configuration
47  */
48 #define CONFIG_PSC_CONSOLE      1           /* console is on PSC1 */
49 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
50 #define CONFIG_SYS_BAUDRATE_TABLE               \
51         { 9600, 19200, 38400, 57600, 115200, 230400 }
52
53 /*
54  * Command line configuration.
55  */
56 #include <config_cmd_default.h>
57
58 #define CONFIG_CMD_BSP
59 #define CONFIG_CMD_CACHE
60 #define CONFIG_CMD_MII
61 #define CONFIG_CMD_REGINFO
62
63 /*
64  * IPB Bus clocking configuration.
65  */
66 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
67 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
68 #ifdef CONFIG_A4M2K
69 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
70 #else
71 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
72 #endif
73
74 /* pass open firmware flat tree */
75 #define CONFIG_OF_LIBFDT
76 #define CONFIG_OF_BOARD_SETUP
77
78 /* maximum size of the flat tree (8K) */
79 #define OF_FLAT_TREE_MAX_SIZE   8192
80
81 #define OF_CPU                  "PowerPC,5200@0"
82 #define OF_SOC                  "soc5200@f0000000"
83 #define OF_TBCLK                (bd->bi_busfreq / 4)
84 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
85
86 /*
87  * NOR flash configuration
88  */
89 #define CONFIG_SYS_FLASH_BASE           0xfc000000
90 #define CONFIG_SYS_FLASH_SIZE           0x02000000
91 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x40000)
92
93 #define CONFIG_SYS_MAX_FLASH_BANKS      1
94 #define CONFIG_SYS_MAX_FLASH_SECT       256
95 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
97 #define CONFIG_SYS_FLASH_LOCK_TOUT      5
98 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000
99 #define CONFIG_SYS_FLASH_PROTECTION
100 #define CONFIG_FLASH_CFI_DRIVER
101 #define CONFIG_SYS_FLASH_CFI
102 #define CONFIG_SYS_FLASH_EMPTY_INFO
103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
104
105 /*
106  * Environment settings
107  */
108 #define CONFIG_ENV_IS_IN_FLASH
109 #define CONFIG_ENV_SIZE         0x10000
110 #define CONFIG_ENV_SECT_SIZE    0x20000
111 #define CONFIG_ENV_OVERWRITE
112
113 /*
114  * Memory map
115  */
116 #define CONFIG_SYS_MBAR                 0xf0000000
117 #define CONFIG_SYS_SDRAM_BASE           0x00000000
118 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
119
120 /* Use SRAM until RAM will be available */
121 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
122 #define CONFIG_SYS_INIT_RAM_END         MPC5XXX_SRAM_SIZE
123
124
125 #define CONFIG_SYS_GBL_DATA_SIZE        128
126 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
127                                          CONFIG_SYS_GBL_DATA_SIZE)
128 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
129
130 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
131
132 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
133 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)
134 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
135
136 /*
137  * Ethernet configuration
138  */
139 #define CONFIG_MPC5xxx_FEC
140 #define CONFIG_MPC5xxx_FEC_MII100
141 #ifdef CONFIG_A4M2K
142 #define CONFIG_PHY_ADDR                 0x01
143 #else
144 #define CONFIG_PHY_ADDR                 0x00
145 #endif
146
147 /*
148  * GPIO configuration
149  */
150
151 /*
152  * GPIO-config depends on failsave-level
153  * failsave 0 means just MPX-config, no digiboard, no fpga
154  *          1 means digiboard ok
155  *          2 means fpga ok
156  */
157
158 #ifdef CONFIG_A4M2K
159 #define CONFIG_SYS_GPS_PORT_CONFIG      0x0005C805
160 #else
161 /* for failsave-level 0 - full failsave */
162 #define CONFIG_SYS_GPS_PORT_CONFIG      0x1005C005
163 /* for failsave-level 1 - only digiboard ok */
164 #define CONFIG_SYS_GPS_PORT_CONFIG_1    0x1005C005
165 /* for failsave-level 2 - all ok */
166 #define CONFIG_SYS_GPS_PORT_CONFIG_2    0x1005C005
167 #endif
168
169 #define CONFIG_WDOG_GPIO_PIN            GPIO_WKUP_7
170 #if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
171 #define CONFIG_HW_WATCHDOG              /* Use external HW-Watchdog     */
172 #endif
173
174 /*
175  * Configuration matrix
176  *                        MSB                          LSB
177  * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
178  * failsave 1  0x1005C005  00010000000001011100000000000101  ( digib.-ver ok )
179  * failsave 2  0x1005C005  00010000000001011100000000000101  ( all ok )
180  *                         || ||| ||  |   ||| |   |   |   |
181  *                         || ||| ||  |   ||| |   |   |   |  bit rev name
182  *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
183  *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
184  *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
185  *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
186  *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
187  *                              +-++--+---+++-+---+---+---+-  5   26 CS6
188  *                                ||  |   ||| |   |   |   |   6   25 ATA
189  *                                ++--+---+++-+---+---+---+-  7   24 ATA
190  *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
191  *                                    |   ||| |   |   |   |   9   22 IRDA
192  *                                    |   ||| |   |   |   |  10   21 IRDA
193  *                                    +---+++-+---+---+---+- 11   20 IRDA
194  *                                        ||| |   |   |   |  12   19 Ether
195  *                                        ||| |   |   |   |  13   18 Ether
196  *                                        ||| |   |   |   |  14   17 Ether
197  *                                        +++-+---+---+---+- 15   16 Ether
198  *                                         ++-+---+---+---+- 16   15 PCI_DIS
199  *                                          +-+---+---+---+- 17   14 USB_SE
200  *                                            |   |   |   |  18   13 USB
201  *                                            +---+---+---+- 19   12 USB
202  *                                                |   |   |  20   11 PSC3
203  *                                                |   |   |  21   10 PSC3
204  *                                                |   |   |  22    9 PSC3
205  *                                                +---+---+- 23    8 PSC3
206  *                                                    |   |  24    7 -
207  *                                                    |   |  25    6 PSC2
208  *                                                    |   |  26    5 PSC2
209  *                                                    +---+- 27    4 PSC2
210  *                                                        |  28    3 -
211  *                                                        |  29    2 PSC1
212  *                                                        |  30    1 PSC1
213  *                                                        +- 31    0 PSC1
214  */
215
216
217 /*
218  * Miscellaneous configurable options
219  */
220 #define CONFIG_SYS_LONGHELP
221 #define CONFIG_SYS_PROMPT               "=> "
222
223 #define CONFIG_CMDLINE_EDITING
224 #define CONFIG_SYS_HUSH_PARSER
225 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
226
227 #if defined(CONFIG_CMD_KGDB)
228 #define CONFIG_SYS_CBSIZE               1024
229 #else
230 #define CONFIG_SYS_CBSIZE               256
231 #endif
232 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
233 #define CONFIG_SYS_MAXARGS              16
234 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
235
236 #define CONFIG_SYS_MEMTEST_START        0x00100000
237 #define CONFIG_SYS_MEMTEST_END          0x00f00000
238
239 #define CONFIG_SYS_LOAD_ADDR            0x00100000
240
241 #define CONFIG_SYS_HZ                   1000
242 #define CONFIG_LOOPW
243 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup*/
244
245 /*
246  * Various low-level settings
247  */
248 #define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
249 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
250
251 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
252 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
253 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
254 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
255
256 #ifdef CONFIG_A4M2K
257 /* external MRAM */
258 #define CONFIG_SYS_CS1_START            0xf1000000
259 #define CONFIG_SYS_CS1_SIZE             (512 << 10)     /* 512KiB MRAM */
260 #endif
261
262 #define CONFIG_SYS_CS2_START            0xe0000000
263 #define CONFIG_SYS_CS2_SIZE             0x00100000
264
265 /* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
266 #define CONFIG_SYS_CS3_START            0xE9000000
267 #ifdef CONFIG_A4M2K
268 #define CONFIG_SYS_CS3_SIZE             0x00100000
269 #else
270 #define CONFIG_SYS_CS3_SIZE             0x00080000
271 #endif
272 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
273 #define CONFIG_SYS_CS3_CFG              0x0032B900
274
275 #ifndef CONFIG_A4M2K
276 /* Diagnosis Interface - see ticket #63 */
277 #define CONFIG_SYS_CS4_START            0xEA000000
278 #define CONFIG_SYS_CS4_SIZE             0x00000001
279 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
280 #define CONFIG_SYS_CS4_CFG              0x0002B900
281 #endif
282
283 /* FPGA master io (64kiB / 1MiB) - see ticket #66 */
284 #define CONFIG_SYS_CS5_START            0xE8000000
285 #ifdef CONFIG_A4M2K
286 #define CONFIG_SYS_CS5_SIZE             0x00100000
287 #else
288 #define CONFIG_SYS_CS5_SIZE             0x00010000
289 #endif
290 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
291 #define CONFIG_SYS_CS5_CFG              0x0032B900
292
293 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2     /* for pci_clk  = 66 MHz */
294 #define CONFIG_SYS_BOOTCS_CFG           0x0006F900
295 #define CONFIG_SYS_CS1_CFG              0x0008FD00
296 #define CONFIG_SYS_CS2_CFG              0x0006F90C
297 #else   /* for pci_clk = 33 MHz */
298 #define CONFIG_SYS_BOOTCS_CFG           0x0002F900
299 #define CONFIG_SYS_CS1_CFG              0x0001FB00
300 #define CONFIG_SYS_CS2_CFG              0x0002F90C
301 #endif
302
303 #define CONFIG_SYS_CS_BURST             0x00000000
304 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
305 /* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
306 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
307 #define CONFIG_SYS_CS_DEADCYCLE         0x33030000
308
309 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
310
311 /*
312  * Environment Configuration
313  */
314
315 #define CONFIG_BOOTDELAY        0       /* -1 disables auto-boot */
316 #undef  CONFIG_BOOTARGS
317 #define CONFIG_ZERO_BOOTDELAY_CHECK
318
319 #define CONFIG_PREBOOT  "echo;" \
320         "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
321         "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
322         "echo"
323
324 #undef  CONFIG_BOOTARGS
325
326 #define CONFIG_SYS_OS_BASE      0xfc080000
327 #define CONFIG_SYS_FDT_BASE     0xfc060000
328
329 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
330         "hostname=" __stringify(CONFIG_HOSTNAME) "\0"                   \
331         "netdev=eth0\0"                                                 \
332         "verify=no\0"                                                   \
333         "loadaddr=200000\0"                                             \
334         "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0"             \
335         "kernel_addr_r=1000000\0"                                       \
336         "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0"               \
337         "fdt_addr_r=1800000\0"                                          \
338         "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"            \
339         "fdtfile=" __stringify(CONFIG_HOSTNAME) "/"                     \
340                 __stringify(CONFIG_HOSTNAME) ".dtb\0"                   \
341         "rootpath=/opt/eldk-5.2.1/powerpc/"                             \
342                 "core-image-minimal-mtdutils-dropbear-generic\0"        \
343         "consoledev=ttyPSC0\0"                                          \
344         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
345                 "nfsroot=${serverip}:${rootpath}\0"                     \
346         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
347         "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \
348         "addip=setenv bootargs ${bootargs} "                            \
349                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
350                 ":${hostname}:${netdev}:off panic=1\0"                  \
351         "addtty=setenv bootargs ${bootargs} "                           \
352                 "console=${consoledev},${baudrate}\0"                   \
353         "flash_nfs=run nfsargs addip addtty;"                           \
354                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
355         "flash_mtd=run mtdargs addip addtty;"                           \
356                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
357         "flash_self=run ramargs addip addtty;"                          \
358                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
359         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
360                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
361                 "run nfsargs addip addtty;"                             \
362                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
363         "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME)           \
364                 "/u-boot-img.bin\0"                                     \
365         "update=protect off fc000000 fc03ffff; "                        \
366                 "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \
367         "upd=run load;run update\0"                                     \
368         "bootdelay=3\0"                                                 \
369         "bootcmd=run net_nfs\0"                                         \
370         ""
371
372 #define CONFIG_BOOTCOMMAND      "run flash_mtd"
373
374 /*
375  * SPL related defines
376  */
377 #define CONFIG_SPL
378 #define CONFIG_SPL_FRAMEWORK
379 #define CONFIG_SPL_BOARD_INIT
380 #define CONFIG_SPL_NOR_SUPPORT
381 #define CONFIG_SPL_TEXT_BASE    0xfc000000
382 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
383 #define CONFIG_SPL_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
384 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* image.c */
385 #define CONFIG_SPL_LIBGENERIC_SUPPORT   /* string.c */
386 #define CONFIG_SPL_SERIAL_SUPPORT
387
388 /* Place BSS for SPL near end of SDRAM */
389 #define CONFIG_SPL_BSS_START_ADDR       ((128 - 1) << 20)
390 #define CONFIG_SPL_BSS_MAX_SIZE         (64 << 10)
391
392 #define CONFIG_SPL_OS_BOOT
393 /* Place patched DT blob (fdt) at this address */
394 #define CONFIG_SYS_SPL_ARGS_ADDR        0x01800000
395
396 /* Settings for real U-Boot to be loaded from NOR flash */
397 #ifndef __ASSEMBLY__
398 extern char __spl_flash_end[];
399 #endif
400 #define CONFIG_SYS_UBOOT_BASE           __spl_flash_end
401 #define CONFIG_SYS_SPL_MAX_LEN          (32 << 10)
402 #define CONFIG_SYS_UBOOT_START          0x1000100
403
404 #endif /* __CONFIG_H */