Merge branch 'master' of git://git.denx.de/u-boot into resolve
[platform/kernel/u-boot.git] / include / configs / a3m071.h
1 /*
2  * Copyright 2012 Stefan Roese <sr@denx.de>
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17
18 #ifndef __CONFIG_H
19 #define __CONFIG_H
20
21 /*
22  * High Level Configuration Options
23  * (easy to change)
24  */
25
26 #define CONFIG_MPC5200
27 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
28 #define CONFIG_A3M071                   /* ... on A3M071 board */
29 #define CONFIG_MPC5200_DDR              /* ... use DDR RAM      */
30
31 #define CONFIG_SYS_TEXT_BASE    0x01000000      /* boot low for 32 MiB boards */
32
33 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
34
35 #define CONFIG_MISC_INIT_R
36 #define CONFIG_SYS_LOWBOOT              /* Enable lowboot       */
37
38 /*
39  * Serial console configuration
40  */
41 #define CONFIG_PSC_CONSOLE      1           /* console is on PSC1 */
42 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
43 #define CONFIG_SYS_BAUDRATE_TABLE               \
44         { 9600, 19200, 38400, 57600, 115200, 230400 }
45
46 /*
47  * Command line configuration.
48  */
49 #include <config_cmd_default.h>
50
51 #define CONFIG_CMD_BSP
52 #define CONFIG_CMD_CACHE
53 #define CONFIG_CMD_DATE
54 #define CONFIG_CMD_EEPROM
55 #define CONFIG_CMD_I2C
56 #define CONFIG_CMD_MII
57 #define CONFIG_CMD_REGINFO
58
59 /*
60  * IPB Bus clocking configuration.
61  */
62 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
63 /* define for 66MHz speed - undef for 33MHz PCI clock speed */
64 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
65
66 /* pass open firmware flat tree */
67 #define CONFIG_OF_LIBFDT
68 #define CONFIG_OF_BOARD_SETUP
69
70 /* maximum size of the flat tree (8K) */
71 #define OF_FLAT_TREE_MAX_SIZE   8192
72
73 #define OF_CPU                  "PowerPC,5200@0"
74 #define OF_SOC                  "soc5200@f0000000"
75 #define OF_TBCLK                (bd->bi_busfreq / 4)
76 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
77
78 /*
79  * I2C configuration
80  */
81 #define CONFIG_HARD_I2C                         /* I2C with hardware support */
82 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
83
84 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
85 #define CONFIG_SYS_I2C_SLAVE            0x7F
86
87 /*
88  * EEPROM configuration
89  */
90 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
91 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
92 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
93 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
94
95 /*
96  * RTC configuration
97  */
98 #define CONFIG_RTC_PCF8563
99 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
100
101 /*
102  * NOR flash configuration
103  */
104 #define CONFIG_SYS_FLASH_BASE           0xfc000000
105 #define CONFIG_SYS_FLASH_SIZE           0x01000000
106 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x40000)
107
108 #define CONFIG_SYS_MAX_FLASH_BANKS      1
109 #define CONFIG_SYS_MAX_FLASH_SECT       256
110 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
111 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
112 #define CONFIG_SYS_FLASH_LOCK_TOUT      5
113 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000
114 #define CONFIG_SYS_FLASH_PROTECTION
115 #define CONFIG_FLASH_CFI_DRIVER
116 #define CONFIG_SYS_FLASH_CFI
117 #define CONFIG_SYS_FLASH_EMPTY_INFO
118 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
119
120 /*
121  * Environment settings
122  */
123 #define CONFIG_ENV_IS_IN_FLASH
124 #define CONFIG_ENV_SIZE         0x10000
125 #define CONFIG_ENV_SECT_SIZE    0x20000
126 #define CONFIG_ENV_OVERWRITE
127
128 /*
129  * Memory map
130  */
131 #define CONFIG_SYS_MBAR                 0xf0000000
132 #define CONFIG_SYS_SDRAM_BASE           0x00000000
133 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
134
135 /* Use SRAM until RAM will be available */
136 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
137 #define CONFIG_SYS_INIT_RAM_END         MPC5XXX_SRAM_SIZE
138
139
140 #define CONFIG_SYS_GBL_DATA_SIZE        128
141 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
142                                          CONFIG_SYS_GBL_DATA_SIZE)
143 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
144
145 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
146
147 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
148 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)
149 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
150
151 /*
152  * Ethernet configuration
153  */
154 #define CONFIG_MPC5xxx_FEC
155 #define CONFIG_MPC5xxx_FEC_MII100
156 #define CONFIG_PHY_ADDR                 0x00
157
158 /*
159  * GPIO configuration
160  */
161
162 /*
163  * GPIO-config depends on failsave-level
164  * failsave 0 means just MPX-config, no digiboard, no fpga
165  *          1 means digiboard ok
166  *          2 means fpga ok
167  */
168
169 /* for failsave-level 0 - full failsave */
170 #define CONFIG_SYS_GPS_PORT_CONFIG      0x1005C005
171 /* for failsave-level 1 - only digiboard ok */
172 #define CONFIG_SYS_GPS_PORT_CONFIG_1    0x1005C005
173 /* for failsave-level 2 - all ok */
174 #define CONFIG_SYS_GPS_PORT_CONFIG_2    0x1005C005
175
176 /*
177  * Configuration matrix
178  *                        MSB                          LSB
179  * failsave 0  0x1005C005  00010000000001011100000001100101  ( full failsave )
180  * failsave 1  0x1005C005  00010000000001011100000001100101  ( digib.-ver ok )
181  * failsave 2  0x1005C005  00010000000001011100000001100101  ( all ok )
182  *                         || ||| ||  |   ||| |   |   |   |
183  *                         || ||| ||  |   ||| |   |   |   |  bit rev name
184  *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
185  *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
186  *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
187  *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
188  *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
189  *                              +-++--+---+++-+---+---+---+-  5   26 CS6
190  *                                ||  |   ||| |   |   |   |   6   25 ATA
191  *                                ++--+---+++-+---+---+---+-  7   24 ATA
192  *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
193  *                                    |   ||| |   |   |   |   9   22 IRDA
194  *                                    |   ||| |   |   |   |  10   21 IRDA
195  *                                    +---+++-+---+---+---+- 11   20 IRDA
196  *                                        ||| |   |   |   |  12   19 Ether
197  *                                        ||| |   |   |   |  13   18 Ether
198  *                                        ||| |   |   |   |  14   17 Ether
199  *                                        +++-+---+---+---+- 15   16 Ether
200  *                                         ++-+---+---+---+- 16   15 PCI_DIS
201  *                                          +-+---+---+---+- 17   14 USB_SE
202  *                                            |   |   |   |  18   13 USB
203  *                                            +---+---+---+- 19   12 USB
204  *                                                |   |   |  20   11 PSC3
205  *                                                |   |   |  21   10 PSC3
206  *                                                |   |   |  22    9 PSC3
207  *                                                +---+---+- 23    8 PSC3
208  *                                                    |   |  24    7 -
209  *                                                    |   |  25    6 PSC2
210  *                                                    |   |  26    5 PSC2
211  *                                                    +---+- 27    4 PSC2
212  *                                                        |  28    3 -
213  *                                                        |  29    2 PSC1
214  *                                                        |  30    1 PSC1
215  *                                                        +- 31    0 PSC1
216  */
217
218
219 /*
220  * Miscellaneous configurable options
221  */
222 #define CONFIG_SYS_LONGHELP
223 #define CONFIG_SYS_PROMPT               "=> "
224
225 #define CONFIG_CMDLINE_EDITING
226 #define CONFIG_SYS_HUSH_PARSER
227 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
228
229 #if defined(CONFIG_CMD_KGDB)
230 #define CONFIG_SYS_CBSIZE               1024
231 #else
232 #define CONFIG_SYS_CBSIZE               256
233 #endif
234 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
235 #define CONFIG_SYS_MAXARGS              16
236 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
237
238 #define CONFIG_SYS_MEMTEST_START        0x00100000
239 #define CONFIG_SYS_MEMTEST_END          0x00f00000
240
241 #define CONFIG_SYS_LOAD_ADDR            0x00100000
242
243 #define CONFIG_SYS_HZ                   1000
244 #define CONFIG_LOOPW
245 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup*/
246
247 /*
248  * Various low-level settings
249  */
250 #define CONFIG_SYS_HID0_INIT            (HID0_ICE | HID0_ICFI)
251 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
252
253 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
254 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
255 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
256 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
257 #define CONFIG_SYS_CS2_START            0xe0000000
258 #define CONFIG_SYS_CS2_SIZE             0x00100000
259
260 /* FPGA slave io (512kiB) - see ticket #66 */
261 #define CONFIG_SYS_CS3_START            0xE9000000
262 #define CONFIG_SYS_CS3_SIZE             0x00080000
263 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
264 #define CONFIG_SYS_CS3_CFG              0x0032B900
265
266 /* Diagnosis Interface - see ticket #63 */
267 #define CONFIG_SYS_CS4_START            0xEA000000
268 #define CONFIG_SYS_CS4_SIZE             0x00000001
269 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
270 #define CONFIG_SYS_CS4_CFG              0x0002B900
271
272 /* FPGA master io (64kiB) - see ticket #66 */
273 #define CONFIG_SYS_CS5_START            0xE8000000
274 #define CONFIG_SYS_CS5_SIZE             0x00010000
275 /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
276 #define CONFIG_SYS_CS5_CFG              0x0032B900
277
278 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2     /* for pci_clk  = 66 MHz */
279 #define CONFIG_SYS_BOOTCS_CFG           0x0006F900
280 #define CONFIG_SYS_CS1_CFG              0x0004FB00
281 #define CONFIG_SYS_CS2_CFG              0x0006F90C
282 #else   /* for pci_clk = 33 MHz */
283 #define CONFIG_SYS_BOOTCS_CFG           0x0002F900
284 #define CONFIG_SYS_CS1_CFG              0x0001FB00
285 #define CONFIG_SYS_CS2_CFG              0x0002F90C
286 #endif
287
288 #define CONFIG_SYS_CS_BURST             0x00000000
289 /* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
290 /* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
291 /* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
292 #define CONFIG_SYS_CS_DEADCYCLE         0x33030000
293
294 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
295
296 /*
297  * Environment Configuration
298  */
299
300 #define CONFIG_BOOTDELAY        0       /* -1 disables auto-boot */
301 #undef  CONFIG_BOOTARGS
302 #define CONFIG_ZERO_BOOTDELAY_CHECK
303
304 #define CONFIG_PREBOOT  "echo;" \
305         "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
306         "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
307         "echo"
308
309 #undef  CONFIG_BOOTARGS
310
311 #define CONFIG_SYS_OS_BASE      0xfc080000
312 #define CONFIG_SYS_FDT_BASE     0xfc060000
313
314 #define xstr(s) str(s)
315 #define str(s)  #s
316
317 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
318         "netdev=eth0\0"                                                 \
319         "verify=no\0"                                                   \
320         "consoledev=ttyPSC0\0"                                          \
321         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
322                 "nfsroot=${serverip}:${rootpath}\0"                     \
323         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
324         "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
325         "addip=setenv bootargs ${bootargs} "                            \
326                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
327                 ":${hostname}:${netdev}:off panic=1\0"                  \
328         "addtty=setenv bootargs ${bootargs} "                           \
329                 "console=${consoledev},${baudrate}\0"                   \
330         "flash_nfs=run nfsargs addip addtty;"                           \
331                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
332         "flash_mtd=run mtdargs addip addtty;"                           \
333                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
334         "flash_self=run ramargs addip addtty;"                          \
335                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"     \
336         "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};"                \
337                 "tftp c00000 ${fdtfile};"                               \
338                 "run nfsargs addip addtty;"                             \
339                 "bootm ${loadaddr} - c00000\0"                          \
340         "load=tftp ${loadaddr} u-boot.bin\0"                            \
341         "update=protect off fc000000 fc03ffff; "                        \
342                 "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
343         "upd=run load;run update\0"                                     \
344         "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0"                       \
345         "fdtfile=dtbFile\0"                                             \
346         "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0"                    \
347         ""
348
349 #define CONFIG_BOOTCOMMAND      "run flash_mtd"
350
351 /*
352  * SPL related defines
353  */
354 #define CONFIG_SPL
355 #define CONFIG_SPL_FRAMEWORK
356 #define CONFIG_SPL_NOR_SUPPORT
357 #define CONFIG_SPL_TEXT_BASE    0xfc000000
358 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
359 #define CONFIG_SPL_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
360 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* image.c */
361 #define CONFIG_SPL_LIBGENERIC_SUPPORT   /* string.c */
362 #define CONFIG_SPL_SERIAL_SUPPORT
363
364 /* Place BSS for SPL near end of SDRAM */
365 #define CONFIG_SPL_BSS_START_ADDR       ((128 - 1) << 20)
366 #define CONFIG_SPL_BSS_MAX_SIZE         (64 << 10)
367
368 #define CONFIG_SPL_OS_BOOT
369 /* Place patched DT blob (fdt) at this address */
370 #define CONFIG_SYS_SPL_ARGS_ADDR        0x01800000
371
372 /* Settings for real U-Boot to be loaded from NOR flash */
373 #ifndef __ASSEMBLY__
374 extern char __spl_flash_end[];
375 #endif
376 #define CONFIG_SYS_UBOOT_BASE           __spl_flash_end
377 #define CONFIG_SYS_SPL_MAX_LEN          (32 << 10)
378 #define CONFIG_SYS_UBOOT_START          0x1000100
379
380 #endif /* __CONFIG_H */