include/configs/UCP1020.h

   1 /*
   2  * Copyright 2013-2015 Arcturus Networks, Inc.
   3  *           http://www.arcturusnetworks.com/products/ucp1020/
   4  * based on include/configs/p1_p2_rdb_pc.h
   5  * original copyright follows:
   6  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * QorIQ uCP1020-xx boards configuration file
  13  */
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_FSL_ELBC
  20 #define CONFIG_PCI
  21 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
  22 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
  23 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  24 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  25 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  26 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  27
  28 #if defined(CONFIG_TARTGET_UCP1020T1)
  29
  30 #define CONFIG_UCP1020_REV_1_3
  31
  32 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
  33 #define CONFIG_P1020
  34
  35 #define CONFIG_TSEC_ENET
  36 #define CONFIG_TSEC1
  37 #define CONFIG_TSEC3
  38 #define CONFIG_HAS_ETH0
  39 #define CONFIG_HAS_ETH1
  40 #define CONFIG_ETHADDR          00:19:D3:FF:FF:FF
  41 #define CONFIG_ETH1ADDR         00:19:D3:FF:FF:FE
  42 #define CONFIG_ETH2ADDR         00:19:D3:FF:FF:FD
  43 #define CONFIG_IPADDR           10.80.41.229
  44 #define CONFIG_SERVERIP         10.80.41.227
  45 #define CONFIG_NETMASK          255.255.252.0
  46 #define CONFIG_ETHPRIME         "eTSEC3"
  47
  48 #ifndef CONFIG_SPI_FLASH
  49 #endif
  50 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  51
  52 #define CONFIG_MMC
  53 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  54
  55 #define CONFIG_LAST_STAGE_INIT
  56
  57 #if !defined(CONFIG_DONGLE)
  58 #define CONFIG_SILENT_CONSOLE
  59 #endif
  60
  61 #endif
  62
  63 #if defined(CONFIG_TARGET_UCP1020)
  64
  65 #define CONFIG_UCP1020
  66 #define CONFIG_UCP1020_REV_1_3
  67
  68 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
  69 #define CONFIG_P1020
  70
  71 #define CONFIG_TSEC_ENET
  72 #define CONFIG_TSEC1
  73 #define CONFIG_TSEC2
  74 #define CONFIG_TSEC3
  75 #define CONFIG_HAS_ETH0
  76 #define CONFIG_HAS_ETH1
  77 #define CONFIG_HAS_ETH2
  78 #define CONFIG_ETHADDR          00:06:3B:FF:FF:FF
  79 #define CONFIG_ETH1ADDR         00:06:3B:FF:FF:FE
  80 #define CONFIG_ETH2ADDR         00:06:3B:FF:FF:FD
  81 #define CONFIG_IPADDR           192.168.1.81
  82 #define CONFIG_IPADDR1          192.168.1.82
  83 #define CONFIG_IPADDR2          192.168.1.83
  84 #define CONFIG_SERVERIP         192.168.1.80
  85 #define CONFIG_GATEWAYIP        102.168.1.1
  86 #define CONFIG_NETMASK          255.255.255.0
  87 #define CONFIG_ETHPRIME         "eTSEC1"
  88
  89 #ifndef CONFIG_SPI_FLASH
  90 #endif
  91 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  92
  93 #define CONFIG_MMC
  94 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  95
  96 #define CONFIG_LAST_STAGE_INIT
  97
  98 #endif
  99
 100 #ifdef CONFIG_SDCARD
 101 #define CONFIG_RAMBOOT_SDCARD
 102 #define CONFIG_SYS_RAMBOOT
 103 #define CONFIG_SYS_EXTRA_ENV_RELOC
 104 #define CONFIG_SYS_TEXT_BASE            0x11000000
 105 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
 106 #endif
 107
 108 #ifdef CONFIG_SPIFLASH
 109 #define CONFIG_RAMBOOT_SPIFLASH
 110 #define CONFIG_SYS_RAMBOOT
 111 #define CONFIG_SYS_EXTRA_ENV_RELOC
 112 #define CONFIG_SYS_TEXT_BASE            0x11000000
 113 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
 114 #endif
 115
 116 #ifndef CONFIG_SYS_TEXT_BASE
 117 #define CONFIG_SYS_TEXT_BASE            0xeff80000
 118 #endif
 119 #define CONFIG_SYS_TEXT_BASE_NOR        0xeff80000
 120
 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 122 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 123 #endif
 124
 125 #ifndef CONFIG_SYS_MONITOR_BASE
 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 127 #endif
 128
 129 /* High Level Configuration Options */
 130 #define CONFIG_BOOKE
 131 #define CONFIG_E500
 132 /* #define CONFIG_MPC85xx */
 133
 134 #define CONFIG_MP
 135
 136 #define CONFIG_FSL_LAW
 137
 138 #define CONFIG_ENV_OVERWRITE
 139
 140 #define CONFIG_CMD_SATA
 141 #define CONFIG_SATA_SIL
 142 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 143 #define CONFIG_LIBATA
 144 #define CONFIG_LBA48
 145
 146 #define CONFIG_SYS_CLK_FREQ     66666666
 147 #define CONFIG_DDR_CLK_FREQ     66666666
 148
 149 #define CONFIG_HWCONFIG
 150
 151 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 152 #define CONFIG_SYS_DTT_BUS_NUM  1       /* The I2C bus for DTT          */
 153 #define CONFIG_DTT_SENSORS      { 0, 1 }        /* Sensor index */
 154 /*
 155  * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
 156  * there will be one entry in this array for each two (dummy) sensors in
 157  * CONFIG_DTT_SENSORS.
 158  *
 159  * For uCP1020 module:
 160  * - only one ADM1021/NCT72
 161  * - i2c addr 0x41
 162  * - conversion rate 0x02 = 0.25 conversions/second
 163  * - ALERT output disabled
 164  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 165  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 166  */
 167 #define CONFIG_SYS_DTT_ADM1021  { { CONFIG_SYS_I2C_NCT72_ADDR, \
 168                                          0x02, 0, 1, 0, 85, 1, 0, 85} }
 169
 170 #define CONFIG_CMD_DTT
 171
 172 /*
 173  * These can be toggled for performance analysis, otherwise use default.
 174  */
 175 #define CONFIG_L2_CACHE
 176 #define CONFIG_BTB
 177
 178 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 179
 180 #define CONFIG_ENABLE_36BIT_PHYS
 181
 182 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 183 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 184 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 185
 186 #define CONFIG_SYS_CCSRBAR              0xffe00000
 187 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 188
 189 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 190        SPL code*/
 191 #ifdef CONFIG_SPL_BUILD
 192 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 193 #endif
 194
 195 /* DDR Setup */
 196 #define CONFIG_DDR_ECC_ENABLE
 197 #define CONFIG_SYS_FSL_DDR3
 198 #ifndef CONFIG_DDR_ECC_ENABLE
 199 #define CONFIG_SYS_DDR_RAW_TIMING
 200 #define CONFIG_DDR_SPD
 201 #endif
 202 #define CONFIG_SYS_SPD_BUS_NUM 1
 203 #undef CONFIG_FSL_DDR_INTERACTIVE
 204
 205 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
 206 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 207 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 208 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 209 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 210
 211 #define CONFIG_NUM_DDR_CONTROLLERS      1
 212 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 213
 214 /* Default settings for DDR3 */
 215 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 216 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 217 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 218 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 219 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 220 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 221
 222 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 223 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 224 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 225 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 226
 227 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 228 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 229 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 230 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 231 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 232 #ifdef CONFIG_DDR_ECC_ENABLE
 233 #define CONFIG_SYS_DDR_CONTROL          0xE70C0000      /* Type = DDR3 & ECC */
 234 #else
 235 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3 */
 236 #endif
 237 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 238 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 239 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 240
 241 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 242 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 243 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 244 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 245 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 246 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 247 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 248 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 249
 250 #undef CONFIG_CLOCKS_IN_MHZ
 251
 252 /*
 253  * Memory map
 254  *
 255  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 256  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1G non-cacheable(PCIe * 2)
 257  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 258  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 256K cacheable
 259  *   (early boot only)
 260  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 261  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 262  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 263  */
 264
 265 /*
 266  * Local Bus Definitions
 267  */
 268 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 269 #define CONFIG_SYS_FLASH_BASE           0xec000000
 270
 271 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 272
 273 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 274         | BR_PS_16 | BR_V)
 275
 276 #define CONFIG_FLASH_OR_PRELIM          0xfc000ff7
 277
 278 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 279 #define CONFIG_SYS_FLASH_QUIET_TEST
 280 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 281
 282 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 283
 284 #undef CONFIG_SYS_FLASH_CHECKSUM
 285 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 286 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 287
 288 #define CONFIG_FLASH_CFI_DRIVER
 289 #define CONFIG_SYS_FLASH_CFI
 290 #define CONFIG_SYS_FLASH_EMPTY_INFO
 291 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 292
 293 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 294
 295 #define CONFIG_SYS_INIT_RAM_LOCK
 296 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 297 /* Initial L1 address */
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 301 /* Size of used area in RAM */
 302 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 303
 304 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 305                                         GENERATED_GBL_DATA_SIZE)
 306 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 307
 308 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)/* Reserve 256 kB for Mon */
 309 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 310
 311 #define CONFIG_SYS_PMC_BASE     0xff980000
 312 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 313 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 314                                         BR_PS_8 | BR_V)
 315 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 316                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 317                                  OR_GPCM_EAD)
 318
 319 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 320 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 321 #ifdef CONFIG_NAND_FSL_ELBC
 322 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 323 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 324 #endif
 325
 326 /* Serial Port - controlled on board with jumper J8
 327  * open - index 2
 328  * shorted - index 1
 329  */
 330 #define CONFIG_CONS_INDEX               1
 331 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 332 #define CONFIG_SYS_NS16550_SERIAL
 333 #define CONFIG_SYS_NS16550_REG_SIZE     1
 334 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 335 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 336 #define CONFIG_NS16550_MIN_FUNCTIONS
 337 #endif
 338
 339 #define CONFIG_SYS_BAUDRATE_TABLE       \
 340         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 341
 342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 344
 345 /* I2C */
 346 #define CONFIG_SYS_I2C
 347 #define CONFIG_SYS_I2C_FSL
 348 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 349 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 350 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 351 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 352 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 353 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 354 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 355 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 356
 357 #define CONFIG_RTC_DS1337
 358 #define CONFIG_SYS_RTC_DS1337_NOOSC
 359 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 360 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 361 #define CONFIG_SYS_I2C_NCT72_ADDR       0x4C
 362 #define CONFIG_SYS_I2C_IDT6V49205B      0x69
 363
 364 /*
 365  * eSPI - Enhanced SPI
 366  */
 367 #define CONFIG_HARD_SPI
 368
 369 #define CONFIG_SF_DEFAULT_SPEED         10000000
 370 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 371
 372 #if defined(CONFIG_PCI)
 373 /*
 374  * General PCI
 375  * Memory space is mapped 1-1, but I/O space must start from 0.
 376  */
 377
 378 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 379 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT CON9"
 380 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 381 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 382 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 383 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 384 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 385 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 386 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 387 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 388
 389 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 390 #define CONFIG_SYS_PCIE1_NAME           "PCIe SLOT CON10"
 391 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 392 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 393 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 394 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 395 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 396 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 398 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 399
 400 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 401 #define CONFIG_CMD_PCI
 402
 403 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 404 #define CONFIG_DOS_PARTITION
 405 #endif /* CONFIG_PCI */
 406
 407 /*
 408  * Environment
 409  */
 410 #ifdef CONFIG_ENV_FIT_UCBOOT
 411
 412 #define CONFIG_ENV_IS_IN_FLASH
 413 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x20000)
 414 #define CONFIG_ENV_SIZE         0x20000
 415 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 416
 417 #else
 418
 419 #define CONFIG_ENV_SPI_BUS      0
 420 #define CONFIG_ENV_SPI_CS       0
 421 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 422 #define CONFIG_ENV_SPI_MODE     0
 423
 424 #ifdef CONFIG_RAMBOOT_SPIFLASH
 425
 426 #define CONFIG_ENV_IS_IN_SPI_FLASH
 427 #define CONFIG_ENV_SIZE         0x3000          /* 12KB */
 428 #define CONFIG_ENV_OFFSET       0x2000          /* 8KB */
 429 #define CONFIG_ENV_SECT_SIZE    0x1000
 430
 431 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
 432 /* Address and size of Redundant Environment Sector     */
 433 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 434 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 435 #endif
 436
 437 #elif defined(CONFIG_RAMBOOT_SDCARD)
 438 #define CONFIG_ENV_IS_IN_MMC
 439 #define CONFIG_FSL_FIXED_MMC_LOCATION
 440 #define CONFIG_ENV_SIZE         0x2000
 441 #define CONFIG_SYS_MMC_ENV_DEV  0
 442
 443 #elif defined(CONFIG_SYS_RAMBOOT)
 444 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 445 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 446 #define CONFIG_ENV_SIZE         0x2000
 447
 448 #else
 449 #define CONFIG_ENV_IS_IN_FLASH
 450 #define CONFIG_ENV_BASE         (CONFIG_SYS_FLASH_BASE)
 451 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 452 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 453 #define CONFIG_ENV_ADDR         (CONFIG_ENV_BASE + 0xC0000)
 454 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
 455 /* Address and size of Redundant Environment Sector     */
 456 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 457 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 458 #endif
 459
 460 #endif
 461
 462 #endif  /* CONFIG_ENV_FIT_UCBOOT */
 463
 464 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 465 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 466
 467 /*
 468  * Command line configuration.
 469  */
 470 #define CONFIG_CMD_IRQ
 471 #define CONFIG_CMD_DATE
 472 #define CONFIG_CMD_IRQ
 473 #define CONFIG_CMD_REGINFO
 474 #define CONFIG_CMD_ERRATA
 475 #define CONFIG_CMD_CRAMFS
 476
 477 /*
 478  * USB
 479  */
 480 #define CONFIG_HAS_FSL_DR_USB
 481
 482 #if defined(CONFIG_HAS_FSL_DR_USB)
 483 #define CONFIG_USB_EHCI
 484
 485 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 486
 487 #ifdef CONFIG_USB_EHCI
 488 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 489 #define CONFIG_USB_EHCI_FSL
 490 #endif
 491 #endif
 492
 493 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 494
 495 #ifdef CONFIG_MMC
 496 #define CONFIG_FSL_ESDHC
 497 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 498 #define CONFIG_MMC_SPI
 499 #define CONFIG_CMD_MMC_SPI
 500 #define CONFIG_GENERIC_MMC
 501 #endif
 502
 503 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
 504 #define CONFIG_DOS_PARTITION
 505 #endif
 506
 507 /* Misc Extra Settings */
 508 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 509
 510 /*
 511  * Miscellaneous configurable options
 512  */
 513 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 514 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 515 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 516 #if defined(CONFIG_CMD_KGDB)
 517 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 518 #else
 519 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 520 #endif
 521 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 522         /* Print Buffer Size */
 523 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 524 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 525 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms tick */
 526
 527 /*
 528  * For booting Linux, the board info and command line data
 529  * have to be in the first 64 MB of memory, since this is
 530  * the maximum mapped by the Linux kernel during initialization.
 531  */
 532 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 533 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 534
 535 #if defined(CONFIG_CMD_KGDB)
 536 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 537 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 538 #endif
 539
 540 /*
 541  * Environment Configuration
 542  */
 543
 544 #if defined(CONFIG_TSEC_ENET)
 545
 546 #if defined(CONFIG_UCP1020_REV_1_2)
 547 #define CONFIG_PHY_MICREL_KSZ9021
 548 #elif defined(CONFIG_UCP1020_REV_1_3)
 549 #define CONFIG_PHY_MICREL_KSZ9031
 550 #else
 551 #error "UCP1020 module revision is not defined !!!"
 552 #endif
 553
 554 #define CONFIG_BOOTP_SERVERIP
 555
 556 #define CONFIG_MII              /* MII PHY management */
 557 #define CONFIG_TSEC1_NAME       "eTSEC1"
 558 #define CONFIG_TSEC2_NAME       "eTSEC2"
 559 #define CONFIG_TSEC3_NAME       "eTSEC3"
 560
 561 #define TSEC1_PHY_ADDR  4
 562 #define TSEC2_PHY_ADDR  0
 563 #define TSEC2_PHY_ADDR_SGMII    0x00
 564 #define TSEC3_PHY_ADDR  6
 565
 566 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 567 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 568 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 569
 570 #define TSEC1_PHYIDX    0
 571 #define TSEC2_PHYIDX    0
 572 #define TSEC3_PHYIDX    0
 573
 574 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 575
 576 #endif
 577
 578 #define CONFIG_HOSTNAME         UCP1020
 579 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 580 #define CONFIG_BOOTFILE         "uImage"
 581 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 582
 583 /* default location for tftp and bootm */
 584 #define CONFIG_LOADADDR         1000000
 585
 586 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 587
 588 #define CONFIG_BAUDRATE 115200
 589
 590 #if defined(CONFIG_DONGLE)
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 593 "bootcmd=run prog_spi_mbrbootcramfs\0"                                  \
 594 "bootfile=uImage\0"                                                     \
 595 "consoledev=ttyS0\0"                                                    \
 596 "cramfsfile=image.cramfs\0"                                             \
 597 "dtbaddr=0x00c00000\0"                                                  \
 598 "dtbfile=image.dtb\0"                                                   \
 599 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 600 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 601 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 602 "fileaddr=0x01000000\0"                                                 \
 603 "filesize=0x00080000\0"                                                 \
 604 "flashmbr=sf probe 0; "                                                 \
 605         "tftp $loadaddr $mbr; "                                         \
 606         "sf erase $mbr_offset +$filesize; "                             \
 607         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 608 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
 609         "protect off $nor_recoveryaddr +$filesize; "                    \
 610         "erase $nor_recoveryaddr +$filesize; "                          \
 611         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
 612         "protect on $nor_recoveryaddr +$filesize\0 "                    \
 613 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
 614         "protect off $nor_ubootaddr +$filesize; "                       \
 615         "erase $nor_ubootaddr +$filesize; "                             \
 616         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
 617         "protect on $nor_ubootaddr +$filesize\0 "                       \
 618 "flashworking=tftp $workingaddr $cramfsfile; "                          \
 619         "protect off $nor_workingaddr +$filesize; "                     \
 620         "erase $nor_workingaddr +$filesize; "                           \
 621         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
 622         "protect on $nor_workingaddr +$filesize\0 "                     \
 623 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 624 "kerneladdr=0x01100000\0"                                               \
 625 "kernelfile=uImage\0"                                                   \
 626 "loadaddr=0x01000000\0"                                                 \
 627 "mbr=uCP1020d.mbr\0"                                                    \
 628 "mbr_offset=0x00000000\0"                                               \
 629 "mmbr=uCP1020Quiet.mbr\0"                                               \
 630 "mmcpart=0:2\0"                                                         \
 631 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
 632         "mmc erase 1 1; "                                               \
 633         "mmc write $loadaddr 1 1\0"                                     \
 634 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; "                \
 635         "mmc erase 0x40 0x400; "                                        \
 636         "mmc write $loadaddr 0x40 0x400\0"                              \
 637 "netdev=eth0\0"                                                         \
 638 "nor_recoveryaddr=0xEC0A0000\0"                                         \
 639 "nor_ubootaddr=0xEFF80000\0"                                            \
 640 "nor_workingaddr=0xECFA0000\0"                                          \
 641 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
 642         " console=$consoledev,$baudrate $othbootargs; "                 \
 643         "run norloadrecovery; "                                         \
 644         "bootm $kerneladdr - $dtbaddr\0"                                \
 645 "norbootworking=setenv bootargs $workingbootargs"                       \
 646         " console=$consoledev,$baudrate $othbootargs; "                 \
 647         "run norloadworking; "                                          \
 648         "bootm $kerneladdr - $dtbaddr\0"                                \
 649 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
 650         "setenv cramfsaddr $nor_recoveryaddr; "                         \
 651         "cramfsload $dtbaddr $dtbfile; "                                \
 652         "cramfsload $kerneladdr $kernelfile\0"                          \
 653 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
 654         "setenv cramfsaddr $nor_workingaddr; "                          \
 655         "cramfsload $dtbaddr $dtbfile; "                                \
 656         "cramfsload $kerneladdr $kernelfile\0"                          \
 657 "prog_spi_mbr=run spi__mbr\0"                                           \
 658 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0"       \
 659 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
 660         "run spi__cramfs\0"                                             \
 661 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 662         " console=$consoledev,$baudrate $othbootargs; "                 \
 663         "tftp $rootfsaddr $rootfsfile; "                                \
 664         "tftp $loadaddr $kernelfile; "                                  \
 665         "tftp $dtbaddr $dtbfile; "                                      \
 666         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 667 "ramdisk_size=120000\0"                                                 \
 668 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 669 "recoveryaddr=0x02F00000\0"                                             \
 670 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
 671 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 672         "mw.l 0xffe0f008 0x00400000\0"                                  \
 673 "rootfsaddr=0x02F00000\0"                                               \
 674 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 675 "rootpath=/opt/nfsroot\0"                                               \
 676 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
 677         "protect off 0xeC000000 +$filesize; "                           \
 678         "erase 0xEC000000 +$filesize; "                                 \
 679         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
 680         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
 681         "protect on 0xeC000000 +$filesize\0"                            \
 682 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
 683         "protect off 0xeFF80000 +$filesize; "                           \
 684         "erase 0xEFF80000 +$filesize; "                                 \
 685         "cp.b $loadaddr 0xEFF80000 $filesize; "                         \
 686         "cmp.b $loadaddr 0xEFF80000 $filesize; "                        \
 687         "protect on 0xeFF80000 +$filesize\0"                            \
 688 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; "                   \
 689         "sf probe 0; sf erase 0x8000 +$filesize; "                      \
 690         "sf write $loadaddr 0x8000 $filesize\0"                         \
 691 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; "             \
 692         "protect off 0xec0a0000 +$filesize; "                           \
 693         "erase 0xeC0A0000 +$filesize; "                                 \
 694         "cp.b $loadaddr 0xeC0A0000 $filesize; "                         \
 695         "protect on 0xec0a0000 +$filesize\0"                            \
 696 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
 697         "sf probe 1; sf erase 0 +$filesize; "                           \
 698         "sf write $loadaddr 0 $filesize\0"                              \
 699 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
 700         "sf probe 0; sf erase 0 +$filesize; "                           \
 701         "sf write $loadaddr 0 $filesize\0"                              \
 702 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 703         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 704         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 705         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 706         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 707         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 708 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 709 "ubootaddr=0x01000000\0"                                                \
 710 "ubootfile=u-boot.bin\0"                                                \
 711 "ubootd=u-boot4dongle.bin\0"                                            \
 712 "upgrade=run flashworking\0"                                            \
 713 "usb_phy_type=ulpi\0 "                                                  \
 714 "workingaddr=0x02F00000\0"                                              \
 715 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
 716
 717 #else
 718
 719 #if defined(CONFIG_UCP1020T1)
 720
 721 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 722 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"  \
 723 "bootfile=uImage\0"                                                     \
 724 "consoledev=ttyS0\0"                                                    \
 725 "cramfsfile=image.cramfs\0"                                             \
 726 "dtbaddr=0x00c00000\0"                                                  \
 727 "dtbfile=image.dtb\0"                                                   \
 728 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 729 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 730 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 731 "fileaddr=0x01000000\0"                                                 \
 732 "filesize=0x00080000\0"                                                 \
 733 "flashmbr=sf probe 0; "                                                 \
 734         "tftp $loadaddr $mbr; "                                         \
 735         "sf erase $mbr_offset +$filesize; "                             \
 736         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 737 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
 738         "protect off $nor_recoveryaddr +$filesize; "                    \
 739         "erase $nor_recoveryaddr +$filesize; "                          \
 740         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
 741         "protect on $nor_recoveryaddr +$filesize\0 "                    \
 742 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
 743         "protect off $nor_ubootaddr +$filesize; "                       \
 744         "erase $nor_ubootaddr +$filesize; "                             \
 745         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
 746         "protect on $nor_ubootaddr +$filesize\0 "                       \
 747 "flashworking=tftp $workingaddr $cramfsfile; "                          \
 748         "protect off $nor_workingaddr +$filesize; "                     \
 749         "erase $nor_workingaddr +$filesize; "                           \
 750         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
 751         "protect on $nor_workingaddr +$filesize\0 "                     \
 752 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 753 "kerneladdr=0x01100000\0"                                               \
 754 "kernelfile=uImage\0"                                                   \
 755 "loadaddr=0x01000000\0"                                                 \
 756 "mbr=uCP1020.mbr\0"                                                     \
 757 "mbr_offset=0x00000000\0"                                               \
 758 "netdev=eth0\0"                                                         \
 759 "nor_recoveryaddr=0xEC0A0000\0"                                         \
 760 "nor_ubootaddr=0xEFF80000\0"                                            \
 761 "nor_workingaddr=0xECFA0000\0"                                          \
 762 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
 763         " console=$consoledev,$baudrate $othbootargs; "                 \
 764         "run norloadrecovery; "                                         \
 765         "bootm $kerneladdr - $dtbaddr\0"                                \
 766 "norbootworking=setenv bootargs $workingbootargs"                       \
 767         " console=$consoledev,$baudrate $othbootargs; "                 \
 768         "run norloadworking; "                                          \
 769         "bootm $kerneladdr - $dtbaddr\0"                                \
 770 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
 771         "setenv cramfsaddr $nor_recoveryaddr; "                         \
 772         "cramfsload $dtbaddr $dtbfile; "                                \
 773         "cramfsload $kerneladdr $kernelfile\0"                          \
 774 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
 775         "setenv cramfsaddr $nor_workingaddr; "                          \
 776         "cramfsload $dtbaddr $dtbfile; "                                \
 777         "cramfsload $kerneladdr $kernelfile\0"                          \
 778 "othbootargs=quiet\0"                                                   \
 779 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 780         " console=$consoledev,$baudrate $othbootargs; "                 \
 781         "tftp $rootfsaddr $rootfsfile; "                                \
 782         "tftp $loadaddr $kernelfile; "                                  \
 783         "tftp $dtbaddr $dtbfile; "                                      \
 784         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 785 "ramdisk_size=120000\0"                                                 \
 786 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 787 "recoveryaddr=0x02F00000\0"                                             \
 788 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
 789 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 790         "mw.l 0xffe0f008 0x00400000\0"                                  \
 791 "rootfsaddr=0x02F00000\0"                                               \
 792 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 793 "rootpath=/opt/nfsroot\0"                                               \
 794 "silent=1\0"                                                            \
 795 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 796         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 797         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 798         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 799         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 800         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 801 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 802 "ubootaddr=0x01000000\0"                                                \
 803 "ubootfile=u-boot.bin\0"                                                \
 804 "upgrade=run flashworking\0"                                            \
 805 "workingaddr=0x02F00000\0"                                              \
 806 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
 807
 808 #else /* For Arcturus Modules */
 809
 810 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 811 "bootcmd=run norkernel\0"                                               \
 812 "bootfile=uImage\0"                                                     \
 813 "consoledev=ttyS0\0"                                                    \
 814 "dtbaddr=0x00c00000\0"                                                  \
 815 "dtbfile=image.dtb\0"                                                   \
 816 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
 817 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
 818 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
 819 "fileaddr=0x01000000\0"                                                 \
 820 "filesize=0x00080000\0"                                                 \
 821 "flashmbr=sf probe 0; "                                                 \
 822         "tftp $loadaddr $mbr; "                                         \
 823         "sf erase $mbr_offset +$filesize; "                             \
 824         "sf write $loadaddr $mbr_offset $filesize\0"                    \
 825 "flashuboot=tftp $loadaddr $ubootfile; "                                \
 826         "protect off $nor_ubootaddr0 +$filesize; "                      \
 827         "erase $nor_ubootaddr0 +$filesize; "                            \
 828         "cp.b $loadaddr $nor_ubootaddr0 $filesize; "                    \
 829         "protect on $nor_ubootaddr0 +$filesize; "                       \
 830         "protect off $nor_ubootaddr1 +$filesize; "                      \
 831         "erase $nor_ubootaddr1 +$filesize; "                            \
 832         "cp.b $loadaddr $nor_ubootaddr1 $filesize; "                    \
 833         "protect on $nor_ubootaddr1 +$filesize\0 "                      \
 834 "format0=protect off $part0base +$part0size; "                          \
 835         "erase $part0base +$part0size\0"                                \
 836 "format1=protect off $part1base +$part1size; "                          \
 837         "erase $part1base +$part1size\0"                                \
 838 "format2=protect off $part2base +$part2size; "                          \
 839         "erase $part2base +$part2size\0"                                \
 840 "format3=protect off $part3base +$part3size; "                          \
 841         "erase $part3base +$part3size\0"                                \
 842 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
 843 "kerneladdr=0x01100000\0"                                               \
 844 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"                 \
 845 "kernelfile=uImage\0"                                                   \
 846 "loadaddr=0x01000000\0"                                                 \
 847 "mbr=uCP1020.mbr\0"                                                     \
 848 "mbr_offset=0x00000000\0"                                               \
 849 "netdev=eth0\0"                                                         \
 850 "nor_ubootaddr0=0xEC000000\0"                                           \
 851 "nor_ubootaddr1=0xEFF80000\0"                                           \
 852 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
 853         "run norkernelload; "                                           \
 854         "bootm $kerneladdr - $dtbaddr\0"                                \
 855 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; "                       \
 856         "setenv cramfsaddr $part0base; "                                \
 857         "cramfsload $dtbaddr $dtbfile; "                                \
 858         "cramfsload $kerneladdr $kernelfile\0"                          \
 859 "part0base=0xEC100000\0"                                                \
 860 "part0size=0x00700000\0"                                                \
 861 "part1base=0xEC800000\0"                                                \
 862 "part1size=0x02000000\0"                                                \
 863 "part2base=0xEE800000\0"                                                \
 864 "part2size=0x00800000\0"                                                \
 865 "part3base=0xEF000000\0"                                                \
 866 "part3size=0x00F80000\0"                                                \
 867 "partENVbase=0xEC080000\0"                                              \
 868 "partENVsize=0x00080000\0"                                              \
 869 "program0=tftp part0-000000.bin; "                                      \
 870         "protect off $part0base +$filesize; "                           \
 871         "erase $part0base +$filesize; "                                 \
 872         "cp.b $loadaddr $part0base $filesize; "                         \
 873         "echo Verifying...; "                                           \
 874         "cmp.b $loadaddr $part0base $filesize\0"                        \
 875 "program1=tftp part1-000000.bin; "                                      \
 876         "protect off $part1base +$filesize; "                           \
 877         "erase $part1base +$filesize; "                                 \
 878         "cp.b $loadaddr $part1base $filesize; "                         \
 879         "echo Verifying...; "                                           \
 880         "cmp.b $loadaddr $part1base $filesize\0"                        \
 881 "program2=tftp part2-000000.bin; "                                      \
 882         "protect off $part2base +$filesize; "                           \
 883         "erase $part2base +$filesize; "                                 \
 884         "cp.b $loadaddr $part2base $filesize; "                         \
 885         "echo Verifying...; "                                           \
 886         "cmp.b $loadaddr $part2base $filesize\0"                        \
 887 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
 888         "  console=$consoledev,$baudrate $othbootargs; "                \
 889         "tftp $rootfsaddr $rootfsfile; "                                \
 890         "tftp $loadaddr $kernelfile; "                                  \
 891         "tftp $dtbaddr $dtbfile; "                                      \
 892         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
 893 "ramdisk_size=120000\0"                                                 \
 894 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
 895 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
 896         "mw.l 0xffe0f008 0x00400000\0"                                  \
 897 "rootfsaddr=0x02F00000\0"                                               \
 898 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
 899 "rootpath=/opt/nfsroot\0"                                               \
 900 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
 901         "sf probe 0; sf erase 0 +$filesize; "                           \
 902         "sf write $loadaddr 0 $filesize\0"                              \
 903 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; "                 \
 904         "protect off 0xeC000000 +$filesize; "                           \
 905         "erase 0xEC000000 +$filesize; "                                 \
 906         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
 907         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
 908         "protect on 0xeC000000 +$filesize\0"                            \
 909 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
 910         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 911         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
 912         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
 913         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
 914         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
 915 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
 916 "ubootfile=u-boot.bin\0"                                                \
 917 "upgrade=run flashuboot\0"                                              \
 918 "usb_phy_type=ulpi\0 "                                                  \
 919 "boot_nfs= "                                                            \
 920         "setenv bootargs root=/dev/nfs rw "                             \
 921         "nfsroot=$serverip:$rootpath "                                  \
 922         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 923         "console=$consoledev,$baudrate $othbootargs;"                   \
 924         "tftp $loadaddr $bootfile;"                                     \
 925         "tftp $fdtaddr $fdtfile;"                                       \
 926         "bootm $loadaddr - $fdtaddr\0"                                  \
 927 "boot_hd = "                                                            \
 928         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "              \
 929         "console=$consoledev,$baudrate $othbootargs;"                   \
 930         "usb start;"                                                    \
 931         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"                   \
 932         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"                     \
 933         "bootm $loadaddr - $fdtaddr\0"                                  \
 934 "boot_usb_fat = "                                                       \
 935         "setenv bootargs root=/dev/ram rw "                             \
 936         "console=$consoledev,$baudrate $othbootargs "                   \
 937         "ramdisk_size=$ramdisk_size;"                                   \
 938         "usb start;"                                                    \
 939         "fatload usb 0:2 $loadaddr $bootfile;"                          \
 940         "fatload usb 0:2 $fdtaddr $fdtfile;"                            \
 941         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"                    \
 942         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
 943 "boot_usb_ext2 = "                                                      \
 944         "setenv bootargs root=/dev/ram rw "                             \
 945         "console=$consoledev,$baudrate $othbootargs "                   \
 946         "ramdisk_size=$ramdisk_size;"                                   \
 947         "usb start;"                                                    \
 948         "ext2load usb 0:4 $loadaddr $bootfile;"                         \
 949         "ext2load usb 0:4 $fdtaddr $fdtfile;"                           \
 950         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"                   \
 951         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
 952 "boot_nor = "                                                           \
 953         "setenv bootargs root=/dev/$jffs2nor rw "                       \
 954         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 955         "bootm $norbootaddr - $norfdtaddr\0 "                           \
 956 "boot_ram = "                                                           \
 957         "setenv bootargs root=/dev/ram rw "                             \
 958         "console=$consoledev,$baudrate $othbootargs "                   \
 959         "ramdisk_size=$ramdisk_size;"                                   \
 960         "tftp $ramdiskaddr $ramdiskfile;"                               \
 961         "tftp $loadaddr $bootfile;"                                     \
 962         "tftp $fdtaddr $fdtfile;"                                       \
 963         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
 964
 965 #endif
 966 #endif
 967
 968 #endif /* __CONFIG_H */