include/configs/TQM834x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2005
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * TQM8349 board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_E300             1       /* E300 Family */
  18
  19 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
  20 #define CONFIG_SYS_IMMR         0xff400000
  21
  22 /* System clock. Primary input clock when in PCI host mode */
  23 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  24
  25 /*
  26  * Local Bus LCRR
  27  *    LCRR:  DLL bypass, Clock divider is 8
  28  *
  29  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  30  *
  31  * External Local Bus rate is
  32  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  33  */
  34 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
  35 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
  36
  37 /* board pre init: do not call, nothing to do */
  38
  39 /* detect the number of flash banks */
  40
  41 /*
  42  * DDR Setup
  43  */
  44                                 /* DDR is system memory*/
  45 #define CONFIG_SYS_DDR_BASE     0x00000000
  46 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  47 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  48 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
  49 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
  50 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
  51
  52 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  53 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  54 #define CONFIG_SYS_MEMTEST_END          0x00100000
  55
  56 /*
  57  * FLASH on the Local Bus
  58  */
  59 #undef CONFIG_SYS_FLASH_CHECKSUM
  60 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
  61 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
  62 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
  63
  64 /*
  65  * FLASH bank number detection
  66  */
  67
  68 /*
  69  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  70  * Flash banks has to be determined at runtime and stored in a gloabl variable
  71  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  72  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  73  * flash_info, and should be made sufficiently large to accomodate the number
  74  * of banks that might actually be detected.  Since most (all?) Flash related
  75  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  76  * the board, it is defined as tqm834x_num_flash_banks.
  77  */
  78 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
  79
  80 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
  81
  82 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  83 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
  84                                 | BR_MS_GPCM \
  85                                 | BR_PS_32 \
  86                                 | BR_V)
  87
  88 /* FLASH timing (0x0000_0c54) */
  89 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
  90                                         | OR_GPCM_ACS_DIV4 \
  91                                         | OR_GPCM_SCY_5 \
  92                                         | OR_GPCM_TRLX)
  93
  94 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
  95
  96 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
  97                                         | CONFIG_SYS_OR_TIMING_FLASH)
  98
  99 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
 100
 101                                         /* Window base at flash base */
 102 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 103
 104 /* disable remaining mappings */
 105 #define CONFIG_SYS_BR1_PRELIM           0x00000000
 106 #define CONFIG_SYS_OR1_PRELIM           0x00000000
 107 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
 108 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
 109
 110 #define CONFIG_SYS_BR2_PRELIM           0x00000000
 111 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 112 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
 113 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
 114
 115 #define CONFIG_SYS_BR3_PRELIM           0x00000000
 116 #define CONFIG_SYS_OR3_PRELIM           0x00000000
 117 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
 118 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
 119
 120 /*
 121  * Monitor config
 122  */
 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 124
 125 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 126 # define CONFIG_SYS_RAMBOOT
 127 #else
 128 # undef  CONFIG_SYS_RAMBOOT
 129 #endif
 130
 131 #define CONFIG_SYS_INIT_RAM_LOCK        1
 132 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
 133 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 134
 135 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 136                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 138
 139                                 /* Reserve 384 kB = 3 sect. for Mon */
 140 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
 141                                 /* Reserve 512 kB for malloc */
 142 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
 143
 144 /*
 145  * Serial Port
 146  */
 147 #define CONFIG_SYS_NS16550_SERIAL
 148 #define CONFIG_SYS_NS16550_REG_SIZE     1
 149 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 150
 151 #define CONFIG_SYS_BAUDRATE_TABLE  \
 152                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 153
 154 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 155 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 156
 157 /*
 158  * I2C
 159  */
 160 #define CONFIG_SYS_I2C
 161 #define CONFIG_SYS_I2C_FSL
 162 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 163 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 164 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 165
 166 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 167 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 168 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
 169 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
 170 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
 171
 172 /* I2C RTC */
 173 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
 174 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
 175
 176 /*
 177  * TSEC
 178  */
 179
 180 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 181 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 182 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 183 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 184
 185 #if defined(CONFIG_TSEC_ENET)
 186
 187 #define CONFIG_TSEC1            1
 188 #define CONFIG_TSEC1_NAME       "TSEC0"
 189 #define CONFIG_TSEC2            1
 190 #define CONFIG_TSEC2_NAME       "TSEC1"
 191 #define TSEC1_PHY_ADDR          2
 192 #define TSEC2_PHY_ADDR          1
 193 #define TSEC1_PHYIDX            0
 194 #define TSEC2_PHYIDX            0
 195 #define TSEC1_FLAGS             TSEC_GIGABIT
 196 #define TSEC2_FLAGS             TSEC_GIGABIT
 197
 198 /* Options are: TSEC[0-1] */
 199 #define CONFIG_ETHPRIME         "TSEC0"
 200
 201 #endif  /* CONFIG_TSEC_ENET */
 202
 203 #if defined(CONFIG_PCI)
 204
 205 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 206
 207 /* PCI1 host bridge */
 208 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
 209 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 210 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 211 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 212                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 213 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 214 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 215 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
 216 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 217 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
 218
 219 #undef CONFIG_EEPRO100
 220 #define CONFIG_EEPRO100
 221 #undef CONFIG_TULIP
 222
 223 #if !defined(CONFIG_PCI_PNP)
 224         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
 225         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
 226         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 227 #endif
 228
 229 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
 230
 231 #endif  /* CONFIG_PCI */
 232
 233 /*
 234  * Environment
 235  */
 236 #define CONFIG_ENV_ADDR         \
 237                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 238 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
 239 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
 240 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 241 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 242
 243 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 244 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 245
 246 /*
 247  * BOOTP options
 248  */
 249 #define CONFIG_BOOTP_BOOTFILESIZE
 250
 251 /*
 252  * Miscellaneous configurable options
 253  */
 254 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 255
 256 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 257
 258 /*
 259  * For booting Linux, the board info and command line data
 260  * have to be in the first 256 MB of memory, since this is
 261  * the maximum mapped by the Linux kernel during initialization.
 262  */
 263                                 /* Initial Memory map for Linux */
 264 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 265
 266 #define CONFIG_SYS_HRCW_LOW (\
 267         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 268         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 269         HRCWL_CSB_TO_CLKIN_4X1 |\
 270         HRCWL_VCO_1X2 |\
 271         HRCWL_CORE_TO_CSB_2X1)
 272
 273 #if defined(PCI_64BIT)
 274 #define CONFIG_SYS_HRCW_HIGH (\
 275         HRCWH_PCI_HOST |\
 276         HRCWH_64_BIT_PCI |\
 277         HRCWH_PCI1_ARBITER_ENABLE |\
 278         HRCWH_PCI2_ARBITER_DISABLE |\
 279         HRCWH_CORE_ENABLE |\
 280         HRCWH_FROM_0X00000100 |\
 281         HRCWH_BOOTSEQ_DISABLE |\
 282         HRCWH_SW_WATCHDOG_DISABLE |\
 283         HRCWH_ROM_LOC_LOCAL_16BIT |\
 284         HRCWH_TSEC1M_IN_GMII |\
 285         HRCWH_TSEC2M_IN_GMII)
 286 #else
 287 #define CONFIG_SYS_HRCW_HIGH (\
 288         HRCWH_PCI_HOST |\
 289         HRCWH_32_BIT_PCI |\
 290         HRCWH_PCI1_ARBITER_ENABLE |\
 291         HRCWH_PCI2_ARBITER_DISABLE |\
 292         HRCWH_CORE_ENABLE |\
 293         HRCWH_FROM_0X00000100 |\
 294         HRCWH_BOOTSEQ_DISABLE |\
 295         HRCWH_SW_WATCHDOG_DISABLE |\
 296         HRCWH_ROM_LOC_LOCAL_16BIT |\
 297         HRCWH_TSEC1M_IN_GMII |\
 298         HRCWH_TSEC2M_IN_GMII)
 299 #endif
 300
 301 /* System IO Config */
 302 #define CONFIG_SYS_SICRH        0
 303 #define CONFIG_SYS_SICRL        SICRL_LDP_A
 304
 305 /* i-cache and d-cache disabled */
 306 #define CONFIG_SYS_HID0_INIT    0x000000000
 307 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
 308                                  HID0_ENABLE_INSTRUCTION_CACHE)
 309 #define CONFIG_SYS_HID2 HID2_HBE
 310
 311 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 312
 313 /* DDR 0 - 512M */
 314 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 315                                 | BATL_PP_RW \
 316                                 | BATL_MEMCOHERENCE)
 317 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 318                                 | BATU_BL_256M \
 319                                 | BATU_VS \
 320                                 | BATU_VP)
 321 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 322                                 | BATL_PP_RW \
 323                                 | BATL_MEMCOHERENCE)
 324 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 325                                 | BATU_BL_256M \
 326                                 | BATU_VS \
 327                                 | BATU_VP)
 328
 329 /* stack in DCACHE @ 512M (no backing mem) */
 330 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
 331                                 | BATL_PP_RW \
 332                                 | BATL_MEMCOHERENCE)
 333 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
 334                                 | BATU_BL_128K \
 335                                 | BATU_VS \
 336                                 | BATU_VP)
 337
 338 /* PCI */
 339 #ifdef CONFIG_PCI
 340 #define CONFIG_PCI_INDIRECT_BRIDGE
 341 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
 342                                 | BATL_PP_RW \
 343                                 | BATL_MEMCOHERENCE)
 344 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
 345                                 | BATU_BL_256M \
 346                                 | BATU_VS \
 347                                 | BATU_VP)
 348 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
 349                                 | BATL_PP_RW \
 350                                 | BATL_MEMCOHERENCE \
 351                                 | BATL_GUARDEDSTORAGE)
 352 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
 353                                 | BATU_BL_256M \
 354                                 | BATU_VS \
 355                                 | BATU_VP)
 356 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
 357                                 | BATL_PP_RW \
 358                                 | BATL_CACHEINHIBIT \
 359                                 | BATL_GUARDEDSTORAGE)
 360 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
 361                                 | BATU_BL_16M \
 362                                 | BATU_VS \
 363                                 | BATU_VP)
 364 #else
 365 #define CONFIG_SYS_IBAT3L       (0)
 366 #define CONFIG_SYS_IBAT3U       (0)
 367 #define CONFIG_SYS_IBAT4L       (0)
 368 #define CONFIG_SYS_IBAT4U       (0)
 369 #define CONFIG_SYS_IBAT5L       (0)
 370 #define CONFIG_SYS_IBAT5U       (0)
 371 #endif
 372
 373 /* IMMRBAR */
 374 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
 375                                 | BATL_PP_RW \
 376                                 | BATL_CACHEINHIBIT \
 377                                 | BATL_GUARDEDSTORAGE)
 378 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
 379                                 | BATU_BL_1M \
 380                                 | BATU_VS \
 381                                 | BATU_VP)
 382
 383 /* FLASH */
 384 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
 385                                 | BATL_PP_RW \
 386                                 | BATL_CACHEINHIBIT \
 387                                 | BATL_GUARDEDSTORAGE)
 388 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
 389                                 | BATU_BL_256M \
 390                                 | BATU_VS \
 391                                 | BATU_VP)
 392
 393 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 394 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 395 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 396 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 397 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 398 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 399 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 400 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 401 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 402 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 403 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 404 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 405 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 406 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 407 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 408 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 409
 410 #if defined(CONFIG_CMD_KGDB)
 411 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 412 #endif
 413
 414 /*
 415  * Environment Configuration
 416  */
 417
 418                                 /* default location for tftp and bootm */
 419 #define CONFIG_LOADADDR         400000
 420
 421 #define CONFIG_PREBOOT  "echo;" \
 422         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 423         "echo"
 424
 425 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 426         "netdev=eth0\0"                                                 \
 427         "hostname=tqm834x\0"                                            \
 428         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 429                 "nfsroot=${serverip}:${rootpath}\0"                     \
 430         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 431         "addip=setenv bootargs ${bootargs} "                            \
 432                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 433                 ":${hostname}:${netdev}:off panic=1\0"                  \
 434         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 435         "flash_nfs_old=run nfsargs addip addcons;"                      \
 436                 "bootm ${kernel_addr}\0"                                \
 437         "flash_nfs=run nfsargs addip addcons;"                          \
 438                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 439         "flash_self_old=run ramargs addip addcons;"                     \
 440                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 441         "flash_self=run ramargs addip addcons;"                         \
 442                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 443         "net_nfs_old=tftp 400000 ${bootfile};"                          \
 444                 "run nfsargs addip addcons;bootm\0"                     \
 445         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 446                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 447                 "run nfsargs addip addcons; "                           \
 448                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 449         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 450         "bootfile=tqm834x/uImage\0"                                     \
 451         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
 452         "kernel_addr_r=400000\0"                                        \
 453         "fdt_addr_r=600000\0"                                           \
 454         "ramdisk_addr_r=800000\0"                                       \
 455         "kernel_addr=800C0000\0"                                        \
 456         "fdt_addr=800A0000\0"                                           \
 457         "ramdisk_addr=80300000\0"                                       \
 458         "u-boot=tqm834x/u-boot.bin\0"                                   \
 459         "load=tftp 200000 ${u-boot}\0"                                  \
 460         "update=protect off 80000000 +${filesize};"                     \
 461                 "era 80000000 +${filesize};"                            \
 462                 "cp.b 200000 80000000 ${filesize}\0"                    \
 463         "upd=run load update\0"                                         \
 464         ""
 465
 466 #define CONFIG_BOOTCOMMAND      "run flash_self"
 467
 468 /*
 469  * JFFS2 partitions
 470  */
 471 /* mtdparts command line support */
 472
 473 /* default mtd partition table */
 474 #endif  /* __CONFIG_H */