1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * TQM8349 board configuration file
15 * High Level Configuration Options
17 #define CONFIG_E300 1 /* E300 Family */
19 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
20 #define CONFIG_SYS_IMMR 0xff400000
24 * LCRR: DLL bypass, Clock divider is 8
26 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
28 * External Local Bus rate is
29 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
31 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
32 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
34 /* board pre init: do not call, nothing to do */
36 /* detect the number of flash banks */
41 /* DDR is system memory*/
42 #define CONFIG_SYS_DDR_BASE 0x00000000
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
44 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
45 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
46 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
47 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
49 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
50 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END 0x00100000
54 * FLASH on the Local Bus
56 #undef CONFIG_SYS_FLASH_CHECKSUM
57 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
58 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
59 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
62 * FLASH bank number detection
66 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
67 * Flash banks has to be determined at runtime and stored in a gloabl variable
68 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
69 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
70 * flash_info, and should be made sufficiently large to accomodate the number
71 * of banks that might actually be detected. Since most (all?) Flash related
72 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
73 * the board, it is defined as tqm834x_num_flash_banks.
75 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
77 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
79 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
80 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
85 /* FLASH timing (0x0000_0c54) */
86 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
91 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
93 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
94 | CONFIG_SYS_OR_TIMING_FLASH)
96 /* disable remaining mappings */
97 #define CONFIG_SYS_BR1_PRELIM 0x00000000
98 #define CONFIG_SYS_OR1_PRELIM 0x00000000
100 #define CONFIG_SYS_BR2_PRELIM 0x00000000
101 #define CONFIG_SYS_OR2_PRELIM 0x00000000
103 #define CONFIG_SYS_BR3_PRELIM 0x00000000
104 #define CONFIG_SYS_OR3_PRELIM 0x00000000
109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
111 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
112 # define CONFIG_SYS_RAMBOOT
114 # undef CONFIG_SYS_RAMBOOT
117 #define CONFIG_SYS_INIT_RAM_LOCK 1
118 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
119 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
121 #define CONFIG_SYS_GBL_DATA_OFFSET \
122 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
123 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125 /* Reserve 384 kB = 3 sect. for Mon */
126 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
127 /* Reserve 512 kB for malloc */
128 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
133 #define CONFIG_SYS_NS16550_SERIAL
134 #define CONFIG_SYS_NS16550_REG_SIZE 1
135 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
137 #define CONFIG_SYS_BAUDRATE_TABLE \
138 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
140 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
141 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
146 #define CONFIG_SYS_I2C
147 #define CONFIG_SYS_I2C_FSL
148 #define CONFIG_SYS_FSL_I2C_SPEED 400000
149 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
150 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
152 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
159 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
160 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
166 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
167 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
168 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
169 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
171 #if defined(CONFIG_TSEC_ENET)
173 #define CONFIG_TSEC1 1
174 #define CONFIG_TSEC1_NAME "TSEC0"
175 #define CONFIG_TSEC2 1
176 #define CONFIG_TSEC2_NAME "TSEC1"
177 #define TSEC1_PHY_ADDR 2
178 #define TSEC2_PHY_ADDR 1
179 #define TSEC1_PHYIDX 0
180 #define TSEC2_PHYIDX 0
181 #define TSEC1_FLAGS TSEC_GIGABIT
182 #define TSEC2_FLAGS TSEC_GIGABIT
184 /* Options are: TSEC[0-1] */
185 #define CONFIG_ETHPRIME "TSEC0"
187 #endif /* CONFIG_TSEC_ENET */
189 #if defined(CONFIG_PCI)
191 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
193 /* PCI1 host bridge */
194 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
195 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
196 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
197 #define CONFIG_SYS_PCI1_MMIO_BASE \
198 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
199 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
200 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
201 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
202 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
203 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
205 #undef CONFIG_EEPRO100
206 #define CONFIG_EEPRO100
209 #if !defined(CONFIG_PCI_PNP)
210 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
211 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
212 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
215 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
217 #endif /* CONFIG_PCI */
222 #define CONFIG_ENV_ADDR \
223 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
224 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
225 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
226 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
227 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
229 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
230 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
235 #define CONFIG_BOOTP_BOOTFILESIZE
238 * Miscellaneous configurable options
240 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
242 #undef CONFIG_WATCHDOG /* watchdog disabled */
245 * For booting Linux, the board info and command line data
246 * have to be in the first 256 MB of memory, since this is
247 * the maximum mapped by the Linux kernel during initialization.
249 /* Initial Memory map for Linux */
250 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
252 /* System IO Config */
253 #define CONFIG_SYS_SICRH 0
254 #define CONFIG_SYS_SICRL SICRL_LDP_A
256 /* i-cache and d-cache disabled */
257 #define CONFIG_SYS_HID0_INIT 0x000000000
258 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
259 HID0_ENABLE_INSTRUCTION_CACHE)
260 #define CONFIG_SYS_HID2 HID2_HBE
264 #define CONFIG_PCI_INDIRECT_BRIDGE
267 #if defined(CONFIG_CMD_KGDB)
268 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
272 * Environment Configuration
275 /* default location for tftp and bootm */
276 #define CONFIG_LOADADDR 400000
278 #define CONFIG_PREBOOT "echo;" \
279 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
282 #define CONFIG_EXTRA_ENV_SETTINGS \
284 "hostname=tqm834x\0" \
285 "nfsargs=setenv bootargs root=/dev/nfs rw " \
286 "nfsroot=${serverip}:${rootpath}\0" \
287 "ramargs=setenv bootargs root=/dev/ram rw\0" \
288 "addip=setenv bootargs ${bootargs} " \
289 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
290 ":${hostname}:${netdev}:off panic=1\0" \
291 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
292 "flash_nfs_old=run nfsargs addip addcons;" \
293 "bootm ${kernel_addr}\0" \
294 "flash_nfs=run nfsargs addip addcons;" \
295 "bootm ${kernel_addr} - ${fdt_addr}\0" \
296 "flash_self_old=run ramargs addip addcons;" \
297 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
298 "flash_self=run ramargs addip addcons;" \
299 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
300 "net_nfs_old=tftp 400000 ${bootfile};" \
301 "run nfsargs addip addcons;bootm\0" \
302 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
303 "tftp ${fdt_addr_r} ${fdt_file}; " \
304 "run nfsargs addip addcons; " \
305 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
306 "rootpath=/opt/eldk/ppc_6xx\0" \
307 "bootfile=tqm834x/uImage\0" \
308 "fdtfile=tqm834x/tqm834x.dtb\0" \
309 "kernel_addr_r=400000\0" \
310 "fdt_addr_r=600000\0" \
311 "ramdisk_addr_r=800000\0" \
312 "kernel_addr=800C0000\0" \
313 "fdt_addr=800A0000\0" \
314 "ramdisk_addr=80300000\0" \
315 "u-boot=tqm834x/u-boot.bin\0" \
316 "load=tftp 200000 ${u-boot}\0" \
317 "update=protect off 80000000 +${filesize};" \
318 "era 80000000 +${filesize};" \
319 "cp.b 200000 80000000 ${filesize}\0" \
320 "upd=run load update\0" \
323 #define CONFIG_BOOTCOMMAND "run flash_self"
328 /* mtdparts command line support */
330 /* default mtd partition table */
331 #endif /* __CONFIG_H */