1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * TQM8349 board configuration file
15 * High Level Configuration Options
17 #define CONFIG_E300 1 /* E300 Family */
19 /* board pre init: do not call, nothing to do */
21 /* detect the number of flash banks */
26 /* DDR is system memory*/
27 #define CONFIG_SYS_SDRAM_BASE 0x00000000
28 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
29 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
30 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
31 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
33 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
34 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
35 #define CONFIG_SYS_MEMTEST_END 0x00100000
38 * FLASH on the Local Bus
40 #undef CONFIG_SYS_FLASH_CHECKSUM
41 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
42 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
43 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
46 * FLASH bank number detection
50 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
51 * Flash banks has to be determined at runtime and stored in a gloabl variable
52 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
53 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
54 * flash_info, and should be made sufficiently large to accomodate the number
55 * of banks that might actually be detected. Since most (all?) Flash related
56 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
57 * the board, it is defined as tqm834x_num_flash_banks.
59 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
61 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
64 /* disable remaining mappings */
65 #define CONFIG_SYS_BR1_PRELIM 0x00000000
66 #define CONFIG_SYS_OR1_PRELIM 0x00000000
68 #define CONFIG_SYS_BR2_PRELIM 0x00000000
69 #define CONFIG_SYS_OR2_PRELIM 0x00000000
71 #define CONFIG_SYS_BR3_PRELIM 0x00000000
72 #define CONFIG_SYS_OR3_PRELIM 0x00000000
77 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
79 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
80 # define CONFIG_SYS_RAMBOOT
82 # undef CONFIG_SYS_RAMBOOT
85 #define CONFIG_SYS_INIT_RAM_LOCK 1
86 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
87 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
89 #define CONFIG_SYS_GBL_DATA_OFFSET \
90 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
91 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
93 /* Reserve 384 kB = 3 sect. for Mon */
94 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
95 /* Reserve 512 kB for malloc */
96 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
101 #define CONFIG_SYS_NS16550_SERIAL
102 #define CONFIG_SYS_NS16550_REG_SIZE 1
103 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
105 #define CONFIG_SYS_BAUDRATE_TABLE \
106 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
108 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
109 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
114 #define CONFIG_SYS_I2C
115 #define CONFIG_SYS_I2C_FSL
116 #define CONFIG_SYS_FSL_I2C_SPEED 400000
117 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
118 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
120 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
121 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
123 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
127 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
128 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
134 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
135 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
136 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
137 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
139 #if defined(CONFIG_TSEC_ENET)
141 #define CONFIG_TSEC1 1
142 #define CONFIG_TSEC1_NAME "TSEC0"
143 #define CONFIG_TSEC2 1
144 #define CONFIG_TSEC2_NAME "TSEC1"
145 #define TSEC1_PHY_ADDR 2
146 #define TSEC2_PHY_ADDR 1
147 #define TSEC1_PHYIDX 0
148 #define TSEC2_PHYIDX 0
149 #define TSEC1_FLAGS TSEC_GIGABIT
150 #define TSEC2_FLAGS TSEC_GIGABIT
152 /* Options are: TSEC[0-1] */
153 #define CONFIG_ETHPRIME "TSEC0"
155 #endif /* CONFIG_TSEC_ENET */
157 #if defined(CONFIG_PCI)
159 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
161 /* PCI1 host bridge */
162 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
163 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
164 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
165 #define CONFIG_SYS_PCI1_MMIO_BASE \
166 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
167 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
168 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
169 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
170 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
171 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
173 #undef CONFIG_EEPRO100
174 #define CONFIG_EEPRO100
177 #if !defined(CONFIG_PCI_PNP)
178 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
179 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
180 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
183 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
185 #endif /* CONFIG_PCI */
190 #define CONFIG_ENV_ADDR \
191 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
192 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
193 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
194 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
195 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
197 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
198 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
203 #define CONFIG_BOOTP_BOOTFILESIZE
206 * Miscellaneous configurable options
208 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
210 #undef CONFIG_WATCHDOG /* watchdog disabled */
213 * For booting Linux, the board info and command line data
214 * have to be in the first 256 MB of memory, since this is
215 * the maximum mapped by the Linux kernel during initialization.
217 /* Initial Memory map for Linux */
218 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
220 /* System IO Config */
221 #define CONFIG_SYS_SICRH 0
222 #define CONFIG_SYS_SICRL SICRL_LDP_A
226 #define CONFIG_PCI_INDIRECT_BRIDGE
229 #if defined(CONFIG_CMD_KGDB)
230 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
234 * Environment Configuration
237 /* default location for tftp and bootm */
238 #define CONFIG_LOADADDR 400000
240 #define CONFIG_PREBOOT "echo;" \
241 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
244 #define CONFIG_EXTRA_ENV_SETTINGS \
246 "hostname=tqm834x\0" \
247 "nfsargs=setenv bootargs root=/dev/nfs rw " \
248 "nfsroot=${serverip}:${rootpath}\0" \
249 "ramargs=setenv bootargs root=/dev/ram rw\0" \
250 "addip=setenv bootargs ${bootargs} " \
251 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
252 ":${hostname}:${netdev}:off panic=1\0" \
253 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
254 "flash_nfs_old=run nfsargs addip addcons;" \
255 "bootm ${kernel_addr}\0" \
256 "flash_nfs=run nfsargs addip addcons;" \
257 "bootm ${kernel_addr} - ${fdt_addr}\0" \
258 "flash_self_old=run ramargs addip addcons;" \
259 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
260 "flash_self=run ramargs addip addcons;" \
261 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
262 "net_nfs_old=tftp 400000 ${bootfile};" \
263 "run nfsargs addip addcons;bootm\0" \
264 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
265 "tftp ${fdt_addr_r} ${fdt_file}; " \
266 "run nfsargs addip addcons; " \
267 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
268 "rootpath=/opt/eldk/ppc_6xx\0" \
269 "bootfile=tqm834x/uImage\0" \
270 "fdtfile=tqm834x/tqm834x.dtb\0" \
271 "kernel_addr_r=400000\0" \
272 "fdt_addr_r=600000\0" \
273 "ramdisk_addr_r=800000\0" \
274 "kernel_addr=800C0000\0" \
275 "fdt_addr=800A0000\0" \
276 "ramdisk_addr=80300000\0" \
277 "u-boot=tqm834x/u-boot.bin\0" \
278 "load=tftp 200000 ${u-boot}\0" \
279 "update=protect off 80000000 +${filesize};" \
280 "era 80000000 +${filesize};" \
281 "cp.b 200000 80000000 ${filesize}\0" \
282 "upd=run load update\0" \
285 #define CONFIG_BOOTCOMMAND "run flash_self"
290 /* mtdparts command line support */
292 /* default mtd partition table */
293 #endif /* __CONFIG_H */