3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * TQM8349 board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
19 #define CONFIG_MPC834x 1 /* MPC834x specific */
20 #define CONFIG_MPC8349 1 /* MPC8349 specific */
22 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
23 #define CONFIG_SYS_IMMR 0xff400000
25 /* System clock. Primary input clock when in PCI host mode */
26 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
30 * LCRR: DLL bypass, Clock divider is 8
32 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
34 * External Local Bus rate is
35 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
37 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
38 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
40 /* board pre init: do not call, nothing to do */
42 /* detect the number of flash banks */
43 #define CONFIG_BOARD_EARLY_INIT_R
48 /* DDR is system memory*/
49 #define CONFIG_SYS_DDR_BASE 0x00000000
50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
51 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
52 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
53 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
54 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
56 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
57 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
58 #define CONFIG_SYS_MEMTEST_END 0x00100000
61 * FLASH on the Local Bus
63 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
64 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
65 #undef CONFIG_SYS_FLASH_CHECKSUM
66 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
67 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
68 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
72 * FLASH bank number detection
76 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
77 * Flash banks has to be determined at runtime and stored in a gloabl variable
78 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
79 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
80 * flash_info, and should be made sufficiently large to accomodate the number
81 * of banks that might actually be detected. Since most (all?) Flash related
82 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
83 * the board, it is defined as tqm834x_num_flash_banks.
85 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
87 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
89 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
90 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
95 /* FLASH timing (0x0000_0c54) */
96 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
101 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
103 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
104 | CONFIG_SYS_OR_TIMING_FLASH)
106 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
108 /* Window base at flash base */
109 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
111 /* disable remaining mappings */
112 #define CONFIG_SYS_BR1_PRELIM 0x00000000
113 #define CONFIG_SYS_OR1_PRELIM 0x00000000
114 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
115 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
117 #define CONFIG_SYS_BR2_PRELIM 0x00000000
118 #define CONFIG_SYS_OR2_PRELIM 0x00000000
119 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
120 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
122 #define CONFIG_SYS_BR3_PRELIM 0x00000000
123 #define CONFIG_SYS_OR3_PRELIM 0x00000000
124 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
125 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
133 # define CONFIG_SYS_RAMBOOT
135 # undef CONFIG_SYS_RAMBOOT
138 #define CONFIG_SYS_INIT_RAM_LOCK 1
139 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
140 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
142 #define CONFIG_SYS_GBL_DATA_OFFSET \
143 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
144 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
146 /* Reserve 384 kB = 3 sect. for Mon */
147 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
148 /* Reserve 512 kB for malloc */
149 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
154 #define CONFIG_SYS_NS16550_SERIAL
155 #define CONFIG_SYS_NS16550_REG_SIZE 1
156 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
158 #define CONFIG_SYS_BAUDRATE_TABLE \
159 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
161 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
162 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
167 #define CONFIG_SYS_I2C
168 #define CONFIG_SYS_I2C_FSL
169 #define CONFIG_SYS_FSL_I2C_SPEED 400000
170 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
171 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
173 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
174 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
180 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
181 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
186 #define CONFIG_TSEC_ENET /* tsec ethernet support */
189 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
190 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
191 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
192 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
194 #if defined(CONFIG_TSEC_ENET)
196 #define CONFIG_TSEC1 1
197 #define CONFIG_TSEC1_NAME "TSEC0"
198 #define CONFIG_TSEC2 1
199 #define CONFIG_TSEC2_NAME "TSEC1"
200 #define TSEC1_PHY_ADDR 2
201 #define TSEC2_PHY_ADDR 1
202 #define TSEC1_PHYIDX 0
203 #define TSEC2_PHYIDX 0
204 #define TSEC1_FLAGS TSEC_GIGABIT
205 #define TSEC2_FLAGS TSEC_GIGABIT
207 /* Options are: TSEC[0-1] */
208 #define CONFIG_ETHPRIME "TSEC0"
210 #endif /* CONFIG_TSEC_ENET */
212 #if defined(CONFIG_PCI)
214 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
216 /* PCI1 host bridge */
217 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
218 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
219 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
220 #define CONFIG_SYS_PCI1_MMIO_BASE \
221 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
222 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
223 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
224 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
225 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
226 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
228 #undef CONFIG_EEPRO100
229 #define CONFIG_EEPRO100
232 #if !defined(CONFIG_PCI_PNP)
233 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
234 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
235 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
238 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
240 #endif /* CONFIG_PCI */
245 #define CONFIG_ENV_ADDR \
246 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
247 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
248 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
249 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
250 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
252 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
253 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
258 #define CONFIG_BOOTP_BOOTFILESIZE
261 * Miscellaneous configurable options
263 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
265 #undef CONFIG_WATCHDOG /* watchdog disabled */
268 * For booting Linux, the board info and command line data
269 * have to be in the first 256 MB of memory, since this is
270 * the maximum mapped by the Linux kernel during initialization.
272 /* Initial Memory map for Linux */
273 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
275 #define CONFIG_SYS_HRCW_LOW (\
276 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
277 HRCWL_DDR_TO_SCB_CLK_1X1 |\
278 HRCWL_CSB_TO_CLKIN_4X1 |\
280 HRCWL_CORE_TO_CSB_2X1)
282 #if defined(PCI_64BIT)
283 #define CONFIG_SYS_HRCW_HIGH (\
286 HRCWH_PCI1_ARBITER_ENABLE |\
287 HRCWH_PCI2_ARBITER_DISABLE |\
289 HRCWH_FROM_0X00000100 |\
290 HRCWH_BOOTSEQ_DISABLE |\
291 HRCWH_SW_WATCHDOG_DISABLE |\
292 HRCWH_ROM_LOC_LOCAL_16BIT |\
293 HRCWH_TSEC1M_IN_GMII |\
294 HRCWH_TSEC2M_IN_GMII)
296 #define CONFIG_SYS_HRCW_HIGH (\
299 HRCWH_PCI1_ARBITER_ENABLE |\
300 HRCWH_PCI2_ARBITER_DISABLE |\
302 HRCWH_FROM_0X00000100 |\
303 HRCWH_BOOTSEQ_DISABLE |\
304 HRCWH_SW_WATCHDOG_DISABLE |\
305 HRCWH_ROM_LOC_LOCAL_16BIT |\
306 HRCWH_TSEC1M_IN_GMII |\
307 HRCWH_TSEC2M_IN_GMII)
310 /* System IO Config */
311 #define CONFIG_SYS_SICRH 0
312 #define CONFIG_SYS_SICRL SICRL_LDP_A
314 /* i-cache and d-cache disabled */
315 #define CONFIG_SYS_HID0_INIT 0x000000000
316 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
317 HID0_ENABLE_INSTRUCTION_CACHE)
318 #define CONFIG_SYS_HID2 HID2_HBE
320 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
323 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
326 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
330 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
333 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
338 /* stack in DCACHE @ 512M (no backing mem) */
339 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
342 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
349 #define CONFIG_PCI_INDIRECT_BRIDGE
350 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
353 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
357 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
359 | BATL_MEMCOHERENCE \
360 | BATL_GUARDEDSTORAGE)
361 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
365 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
367 | BATL_CACHEINHIBIT \
368 | BATL_GUARDEDSTORAGE)
369 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
374 #define CONFIG_SYS_IBAT3L (0)
375 #define CONFIG_SYS_IBAT3U (0)
376 #define CONFIG_SYS_IBAT4L (0)
377 #define CONFIG_SYS_IBAT4U (0)
378 #define CONFIG_SYS_IBAT5L (0)
379 #define CONFIG_SYS_IBAT5U (0)
383 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
385 | BATL_CACHEINHIBIT \
386 | BATL_GUARDEDSTORAGE)
387 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
393 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
395 | BATL_CACHEINHIBIT \
396 | BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
402 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
403 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
404 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
405 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
406 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
407 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
408 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
409 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
410 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
411 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
412 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
413 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
414 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
415 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
416 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
417 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
419 #if defined(CONFIG_CMD_KGDB)
420 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
424 * Environment Configuration
427 /* default location for tftp and bootm */
428 #define CONFIG_LOADADDR 400000
430 #define CONFIG_PREBOOT "echo;" \
431 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
434 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "hostname=tqm834x\0" \
437 "nfsargs=setenv bootargs root=/dev/nfs rw " \
438 "nfsroot=${serverip}:${rootpath}\0" \
439 "ramargs=setenv bootargs root=/dev/ram rw\0" \
440 "addip=setenv bootargs ${bootargs} " \
441 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
442 ":${hostname}:${netdev}:off panic=1\0" \
443 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
444 "flash_nfs_old=run nfsargs addip addcons;" \
445 "bootm ${kernel_addr}\0" \
446 "flash_nfs=run nfsargs addip addcons;" \
447 "bootm ${kernel_addr} - ${fdt_addr}\0" \
448 "flash_self_old=run ramargs addip addcons;" \
449 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
450 "flash_self=run ramargs addip addcons;" \
451 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
452 "net_nfs_old=tftp 400000 ${bootfile};" \
453 "run nfsargs addip addcons;bootm\0" \
454 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
455 "tftp ${fdt_addr_r} ${fdt_file}; " \
456 "run nfsargs addip addcons; " \
457 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
458 "rootpath=/opt/eldk/ppc_6xx\0" \
459 "bootfile=tqm834x/uImage\0" \
460 "fdtfile=tqm834x/tqm834x.dtb\0" \
461 "kernel_addr_r=400000\0" \
462 "fdt_addr_r=600000\0" \
463 "ramdisk_addr_r=800000\0" \
464 "kernel_addr=800C0000\0" \
465 "fdt_addr=800A0000\0" \
466 "ramdisk_addr=80300000\0" \
467 "u-boot=tqm834x/u-boot.bin\0" \
468 "load=tftp 200000 ${u-boot}\0" \
469 "update=protect off 80000000 +${filesize};" \
470 "era 80000000 +${filesize};" \
471 "cp.b 200000 80000000 ${filesize}\0" \
472 "upd=run load update\0" \
475 #define CONFIG_BOOTCOMMAND "run flash_self"
480 /* mtdparts command line support */
481 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
482 #define CONFIG_FLASH_CFI_MTD
484 /* default mtd partition table */
485 #endif /* __CONFIG_H */