include/configs/TQM834x.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * TQM8349 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19 #define CONFIG_MPC834x          1       /* MPC834x specific */
  20 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  21 #define CONFIG_TQM834X          1       /* TQM834X board specific */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x80000000
  24
  25 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
  26 #define CONFIG_SYS_IMMR         0xff400000
  27
  28 /* System clock. Primary input clock when in PCI host mode */
  29 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  30
  31 /*
  32  * Local Bus LCRR
  33  *    LCRR:  DLL bypass, Clock divider is 8
  34  *
  35  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  36  *
  37  * External Local Bus rate is
  38  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  39  */
  40 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
  41 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
  42
  43 /* board pre init: do not call, nothing to do */
  44
  45 /* detect the number of flash banks */
  46 #define CONFIG_BOARD_EARLY_INIT_R
  47
  48 /*
  49  * DDR Setup
  50  */
  51                                 /* DDR is system memory*/
  52 #define CONFIG_SYS_DDR_BASE     0x00000000
  53 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  55 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
  56 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
  57 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
  58
  59 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  60 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  61 #define CONFIG_SYS_MEMTEST_END          0x00100000
  62
  63 /*
  64  * FLASH on the Local Bus
  65  */
  66 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
  67 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
  68 #undef CONFIG_SYS_FLASH_CHECKSUM
  69 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
  70 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
  71 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
  72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  73
  74 /*
  75  * FLASH bank number detection
  76  */
  77
  78 /*
  79  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  80  * Flash banks has to be determined at runtime and stored in a gloabl variable
  81  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  82  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  83  * flash_info, and should be made sufficiently large to accomodate the number
  84  * of banks that might actually be detected.  Since most (all?) Flash related
  85  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  86  * the board, it is defined as tqm834x_num_flash_banks.
  87  */
  88 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
  89
  90 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
  91
  92 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  93 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
  94                                 | BR_MS_GPCM \
  95                                 | BR_PS_32 \
  96                                 | BR_V)
  97
  98 /* FLASH timing (0x0000_0c54) */
  99 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
 100                                         | OR_GPCM_ACS_DIV4 \
 101                                         | OR_GPCM_SCY_5 \
 102                                         | OR_GPCM_TRLX)
 103
 104 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
 105
 106 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
 107                                         | CONFIG_SYS_OR_TIMING_FLASH)
 108
 109 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
 110
 111                                         /* Window base at flash base */
 112 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 113
 114 /* disable remaining mappings */
 115 #define CONFIG_SYS_BR1_PRELIM           0x00000000
 116 #define CONFIG_SYS_OR1_PRELIM           0x00000000
 117 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
 118 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
 119
 120 #define CONFIG_SYS_BR2_PRELIM           0x00000000
 121 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 122 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
 123 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
 124
 125 #define CONFIG_SYS_BR3_PRELIM           0x00000000
 126 #define CONFIG_SYS_OR3_PRELIM           0x00000000
 127 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
 128 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
 129
 130 /*
 131  * Monitor config
 132  */
 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 134
 135 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 136 # define CONFIG_SYS_RAMBOOT
 137 #else
 138 # undef  CONFIG_SYS_RAMBOOT
 139 #endif
 140
 141 #define CONFIG_SYS_INIT_RAM_LOCK        1
 142 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
 143 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 144
 145 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 146                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 147 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 148
 149                                 /* Reserve 384 kB = 3 sect. for Mon */
 150 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
 151                                 /* Reserve 512 kB for malloc */
 152 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
 153
 154 /*
 155  * Serial Port
 156  */
 157 #define CONFIG_CONS_INDEX       1
 158 #define CONFIG_SYS_NS16550_SERIAL
 159 #define CONFIG_SYS_NS16550_REG_SIZE     1
 160 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 161
 162 #define CONFIG_SYS_BAUDRATE_TABLE  \
 163                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 164
 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 167
 168 /*
 169  * I2C
 170  */
 171 #define CONFIG_SYS_I2C
 172 #define CONFIG_SYS_I2C_FSL
 173 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 174 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 175 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 176
 177 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 178 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
 180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
 182
 183 /* I2C RTC */
 184 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
 185 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
 186
 187 /*
 188  * TSEC
 189  */
 190 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 191 #define CONFIG_MII
 192
 193 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 194 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 195 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 196 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 197
 198 #if defined(CONFIG_TSEC_ENET)
 199
 200 #define CONFIG_TSEC1            1
 201 #define CONFIG_TSEC1_NAME       "TSEC0"
 202 #define CONFIG_TSEC2            1
 203 #define CONFIG_TSEC2_NAME       "TSEC1"
 204 #define TSEC1_PHY_ADDR          2
 205 #define TSEC2_PHY_ADDR          1
 206 #define TSEC1_PHYIDX            0
 207 #define TSEC2_PHYIDX            0
 208 #define TSEC1_FLAGS             TSEC_GIGABIT
 209 #define TSEC2_FLAGS             TSEC_GIGABIT
 210
 211 /* Options are: TSEC[0-1] */
 212 #define CONFIG_ETHPRIME         "TSEC0"
 213
 214 #endif  /* CONFIG_TSEC_ENET */
 215
 216 #if defined(CONFIG_PCI)
 217
 218 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 219
 220 /* PCI1 host bridge */
 221 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
 222 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 223 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 224 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 225                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 226 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 227 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 228 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
 229 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 230 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
 231
 232 #undef CONFIG_EEPRO100
 233 #define CONFIG_EEPRO100
 234 #undef CONFIG_TULIP
 235
 236 #if !defined(CONFIG_PCI_PNP)
 237         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
 238         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
 239         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 240 #endif
 241
 242 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
 243
 244 #endif  /* CONFIG_PCI */
 245
 246 /*
 247  * Environment
 248  */
 249 #define CONFIG_ENV_ADDR         \
 250                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 251 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
 252 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
 253 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 254 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 255
 256 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 257 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 258
 259 /*
 260  * BOOTP options
 261  */
 262 #define CONFIG_BOOTP_BOOTFILESIZE
 263 #define CONFIG_BOOTP_BOOTPATH
 264 #define CONFIG_BOOTP_GATEWAY
 265 #define CONFIG_BOOTP_HOSTNAME
 266
 267 /*
 268  * Miscellaneous configurable options
 269  */
 270 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 271 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 272
 273 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 274 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 275
 276                                 /* Print Buffer Size */
 277 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 278 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 279                                 /* Boot Argument Buffer Size */
 280 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 281
 282 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 256 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289                                 /* Initial Memory map for Linux */
 290 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 291
 292 #define CONFIG_SYS_HRCW_LOW (\
 293         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 294         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 295         HRCWL_CSB_TO_CLKIN_4X1 |\
 296         HRCWL_VCO_1X2 |\
 297         HRCWL_CORE_TO_CSB_2X1)
 298
 299 #if defined(PCI_64BIT)
 300 #define CONFIG_SYS_HRCW_HIGH (\
 301         HRCWH_PCI_HOST |\
 302         HRCWH_64_BIT_PCI |\
 303         HRCWH_PCI1_ARBITER_ENABLE |\
 304         HRCWH_PCI2_ARBITER_DISABLE |\
 305         HRCWH_CORE_ENABLE |\
 306         HRCWH_FROM_0X00000100 |\
 307         HRCWH_BOOTSEQ_DISABLE |\
 308         HRCWH_SW_WATCHDOG_DISABLE |\
 309         HRCWH_ROM_LOC_LOCAL_16BIT |\
 310         HRCWH_TSEC1M_IN_GMII |\
 311         HRCWH_TSEC2M_IN_GMII)
 312 #else
 313 #define CONFIG_SYS_HRCW_HIGH (\
 314         HRCWH_PCI_HOST |\
 315         HRCWH_32_BIT_PCI |\
 316         HRCWH_PCI1_ARBITER_ENABLE |\
 317         HRCWH_PCI2_ARBITER_DISABLE |\
 318         HRCWH_CORE_ENABLE |\
 319         HRCWH_FROM_0X00000100 |\
 320         HRCWH_BOOTSEQ_DISABLE |\
 321         HRCWH_SW_WATCHDOG_DISABLE |\
 322         HRCWH_ROM_LOC_LOCAL_16BIT |\
 323         HRCWH_TSEC1M_IN_GMII |\
 324         HRCWH_TSEC2M_IN_GMII)
 325 #endif
 326
 327 /* System IO Config */
 328 #define CONFIG_SYS_SICRH        0
 329 #define CONFIG_SYS_SICRL        SICRL_LDP_A
 330
 331 /* i-cache and d-cache disabled */
 332 #define CONFIG_SYS_HID0_INIT    0x000000000
 333 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
 334                                  HID0_ENABLE_INSTRUCTION_CACHE)
 335 #define CONFIG_SYS_HID2 HID2_HBE
 336
 337 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 338
 339 /* DDR 0 - 512M */
 340 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 341                                 | BATL_PP_RW \
 342                                 | BATL_MEMCOHERENCE)
 343 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 344                                 | BATU_BL_256M \
 345                                 | BATU_VS \
 346                                 | BATU_VP)
 347 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 348                                 | BATL_PP_RW \
 349                                 | BATL_MEMCOHERENCE)
 350 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 351                                 | BATU_BL_256M \
 352                                 | BATU_VS \
 353                                 | BATU_VP)
 354
 355 /* stack in DCACHE @ 512M (no backing mem) */
 356 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
 357                                 | BATL_PP_RW \
 358                                 | BATL_MEMCOHERENCE)
 359 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
 360                                 | BATU_BL_128K \
 361                                 | BATU_VS \
 362                                 | BATU_VP)
 363
 364 /* PCI */
 365 #ifdef CONFIG_PCI
 366 #define CONFIG_PCI_INDIRECT_BRIDGE
 367 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
 368                                 | BATL_PP_RW \
 369                                 | BATL_MEMCOHERENCE)
 370 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
 371                                 | BATU_BL_256M \
 372                                 | BATU_VS \
 373                                 | BATU_VP)
 374 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
 375                                 | BATL_PP_RW \
 376                                 | BATL_MEMCOHERENCE \
 377                                 | BATL_GUARDEDSTORAGE)
 378 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
 379                                 | BATU_BL_256M \
 380                                 | BATU_VS \
 381                                 | BATU_VP)
 382 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
 383                                 | BATL_PP_RW \
 384                                 | BATL_CACHEINHIBIT \
 385                                 | BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
 387                                 | BATU_BL_16M \
 388                                 | BATU_VS \
 389                                 | BATU_VP)
 390 #else
 391 #define CONFIG_SYS_IBAT3L       (0)
 392 #define CONFIG_SYS_IBAT3U       (0)
 393 #define CONFIG_SYS_IBAT4L       (0)
 394 #define CONFIG_SYS_IBAT4U       (0)
 395 #define CONFIG_SYS_IBAT5L       (0)
 396 #define CONFIG_SYS_IBAT5U       (0)
 397 #endif
 398
 399 /* IMMRBAR */
 400 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
 401                                 | BATL_PP_RW \
 402                                 | BATL_CACHEINHIBIT \
 403                                 | BATL_GUARDEDSTORAGE)
 404 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
 405                                 | BATU_BL_1M \
 406                                 | BATU_VS \
 407                                 | BATU_VP)
 408
 409 /* FLASH */
 410 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
 411                                 | BATL_PP_RW \
 412                                 | BATL_CACHEINHIBIT \
 413                                 | BATL_GUARDEDSTORAGE)
 414 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
 415                                 | BATU_BL_256M \
 416                                 | BATU_VS \
 417                                 | BATU_VP)
 418
 419 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 420 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 421 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 422 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 423 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 424 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 425 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 426 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 427 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 428 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 429 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 430 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 431 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 432 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 433 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 434 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 435
 436 #if defined(CONFIG_CMD_KGDB)
 437 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 438 #endif
 439
 440 /*
 441  * Environment Configuration
 442  */
 443
 444                                 /* default location for tftp and bootm */
 445 #define CONFIG_LOADADDR         400000
 446
 447 #define CONFIG_PREBOOT  "echo;" \
 448         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 449         "echo"
 450
 451 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 452         "netdev=eth0\0"                                                 \
 453         "hostname=tqm834x\0"                                            \
 454         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 455                 "nfsroot=${serverip}:${rootpath}\0"                     \
 456         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 457         "addip=setenv bootargs ${bootargs} "                            \
 458                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 459                 ":${hostname}:${netdev}:off panic=1\0"                  \
 460         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 461         "flash_nfs_old=run nfsargs addip addcons;"                      \
 462                 "bootm ${kernel_addr}\0"                                \
 463         "flash_nfs=run nfsargs addip addcons;"                          \
 464                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 465         "flash_self_old=run ramargs addip addcons;"                     \
 466                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 467         "flash_self=run ramargs addip addcons;"                         \
 468                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 469         "net_nfs_old=tftp 400000 ${bootfile};"                          \
 470                 "run nfsargs addip addcons;bootm\0"                     \
 471         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 472                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 473                 "run nfsargs addip addcons; "                           \
 474                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 475         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 476         "bootfile=tqm834x/uImage\0"                                     \
 477         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
 478         "kernel_addr_r=400000\0"                                        \
 479         "fdt_addr_r=600000\0"                                           \
 480         "ramdisk_addr_r=800000\0"                                       \
 481         "kernel_addr=800C0000\0"                                        \
 482         "fdt_addr=800A0000\0"                                           \
 483         "ramdisk_addr=80300000\0"                                       \
 484         "u-boot=tqm834x/u-boot.bin\0"                                   \
 485         "load=tftp 200000 ${u-boot}\0"                                  \
 486         "update=protect off 80000000 +${filesize};"                     \
 487                 "era 80000000 +${filesize};"                            \
 488                 "cp.b 200000 80000000 ${filesize}\0"                    \
 489         "upd=run load update\0"                                         \
 490         ""
 491
 492 #define CONFIG_BOOTCOMMAND      "run flash_self"
 493
 494 /*
 495  * JFFS2 partitions
 496  */
 497 /* mtdparts command line support */
 498 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 499 #define CONFIG_FLASH_CFI_MTD
 500 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
 501
 502 /* default mtd partition table */
 503 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
 504                                                 "1m(kernel),2m(initrd)," \
 505                                                 "-(user);" \
 506
 507 #endif  /* __CONFIG_H */