1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
38 #ifndef CONFIG_SPL_BUILD
39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #endif /* CONFIG_RAMBOOT_PBL */
53 #define CONFIG_DDR_ECC
55 /* High Level Configuration Options */
56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1 /* PCIE controller 1 */
65 #define CONFIG_PCIE2 /* PCIE controller 2 */
66 #define CONFIG_PCIE3 /* PCIE controller 3 */
67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_SYS_CACHE_STASHING
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
76 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79 #define CONFIG_ENABLE_36BIT_PHYS
82 * Config the L3 Cache as L3 SRAM
84 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
85 #define CONFIG_SYS_L3_SIZE (512 << 10)
86 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
87 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
88 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
89 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
90 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
92 #define CONFIG_SYS_DCSRBAR 0xf0000000
93 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
98 #define CONFIG_VERY_BIG_RAM
99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
103 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
105 #define CONFIG_DDR_SPD
110 #define CONFIG_SYS_FLASH_BASE 0xe0000000
111 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
113 #ifdef CONFIG_SPL_BUILD
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
119 #define CONFIG_HWCONFIG
121 /* define to use L1 as initial stack */
122 #define CONFIG_L1_INIT_RAM
123 #define CONFIG_SYS_INIT_RAM_LOCK
124 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
127 /* The assembler doesn't like typecast */
128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
129 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
130 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
131 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
134 GENERATED_GBL_DATA_SIZE)
135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
137 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
138 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
140 /* Serial Port - controlled on board with jumper J8
144 #define CONFIG_SYS_NS16550_SERIAL
145 #define CONFIG_SYS_NS16550_REG_SIZE 1
146 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
148 #define CONFIG_SYS_BAUDRATE_TABLE \
149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
160 * Memory space is mapped 1-1, but I/O space must start from 0.
163 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
164 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
165 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
166 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
167 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
169 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
170 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
171 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
172 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
173 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
175 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
176 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
177 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
178 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
179 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
181 /* controller 4, Base address 203000 */
182 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
183 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
184 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
187 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
188 #endif /* CONFIG_PCI */
191 #ifdef CONFIG_FSL_SATA_V2
192 #define CONFIG_SYS_SATA_MAX_DEVICE 2
194 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
195 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
197 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
198 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
203 #ifdef CONFIG_FMAN_ENET
204 #define CONFIG_ETHPRIME "FM1@DTSEC1"
210 #define CONFIG_LOADS_ECHO /* echo on for serial download */
211 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
214 * Miscellaneous configurable options
216 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
219 * For booting Linux, the board info and command line data
220 * have to be in the first 64 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
223 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
224 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
226 #ifdef CONFIG_CMD_KGDB
227 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
231 * Environment Configuration
233 #define CONFIG_ROOTPATH "/opt/nfsroot"
234 #define CONFIG_BOOTFILE "uImage"
235 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
237 /* default location for tftp and bootm */
238 #define CONFIG_LOADADDR 1000000
240 #define CONFIG_HVBOOT \
241 "setenv bootargs config-addr=0x60000000; " \
242 "bootm 0x01000000 - 0x00f00000"
244 #define CONFIG_SYS_CLK_FREQ 66666666
245 #define CONFIG_DDR_CLK_FREQ 133333333
248 unsigned long get_board_sys_clk(void);
249 unsigned long get_board_ddr_clk(void);
255 #define CONFIG_SYS_SPD_BUS_NUM 0
256 #define SPD_EEPROM_ADDRESS1 0x52
257 #define SPD_EEPROM_ADDRESS2 0x54
258 #define SPD_EEPROM_ADDRESS3 0x56
259 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
260 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
265 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
266 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
268 CSPR_PORT_SIZE_16 | \
271 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
272 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
273 CSPR_PORT_SIZE_16 | \
276 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
277 /* NOR Flash Timing Params */
278 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
280 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
281 FTIM0_NOR_TEADC(0x5) | \
282 FTIM0_NOR_TEAHC(0x5))
283 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
284 FTIM1_NOR_TRAD_NOR(0x1A) |\
285 FTIM1_NOR_TSEQRAD_NOR(0x13))
286 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
287 FTIM2_NOR_TCH(0x4) | \
288 FTIM2_NOR_TWPH(0x0E) | \
290 #define CONFIG_SYS_NOR_FTIM3 0x0
292 #define CONFIG_SYS_FLASH_QUIET_TEST
293 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
295 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
296 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
297 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
298 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
300 #define CONFIG_SYS_FLASH_EMPTY_INFO
301 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
302 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
304 /* NAND Flash on IFC */
305 #define CONFIG_NAND_FSL_IFC
306 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
307 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
308 #define CONFIG_SYS_NAND_BASE 0xff800000
309 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
311 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
312 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
313 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
314 | CSPR_MSEL_NAND /* MSEL = NAND */ \
316 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
318 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
319 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
320 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
321 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
322 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
323 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
324 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
326 #define CONFIG_SYS_NAND_ONFI_DETECTION
328 /* ONFI NAND Flash mode0 Timing Params */
329 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
330 FTIM0_NAND_TWP(0x18) | \
331 FTIM0_NAND_TWCHT(0x07) | \
332 FTIM0_NAND_TWH(0x0a))
333 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
334 FTIM1_NAND_TWBE(0x39) | \
335 FTIM1_NAND_TRR(0x0e) | \
336 FTIM1_NAND_TRP(0x18))
337 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
338 FTIM2_NAND_TREH(0x0a) | \
339 FTIM2_NAND_TWHRE(0x1e))
340 #define CONFIG_SYS_NAND_FTIM3 0x0
342 #define CONFIG_SYS_NAND_DDR_LAW 11
343 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
344 #define CONFIG_SYS_MAX_NAND_DEVICE 1
346 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
348 #if defined(CONFIG_MTD_RAW_NAND)
349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
366 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
367 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
368 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
369 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
370 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
371 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
372 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
373 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
374 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
375 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
376 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
377 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
378 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
379 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
380 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
381 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
383 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
384 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
385 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
386 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
387 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
388 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
389 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
390 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
393 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
394 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
395 #define CONFIG_SYS_CSPR3_EXT (0xf)
396 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
401 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
402 #define CONFIG_SYS_CSOR3 0x0
404 /* CPLD Timing parameters for IFC CS3 */
405 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
406 FTIM0_GPCM_TEADC(0x0e) | \
407 FTIM0_GPCM_TEAHC(0x0e))
408 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
409 FTIM1_GPCM_TRAD(0x1f))
410 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
411 FTIM2_GPCM_TCH(0x8) | \
412 FTIM2_GPCM_TWP(0x1f))
413 #define CONFIG_SYS_CS3_FTIM3 0x0
415 #if defined(CONFIG_RAMBOOT_PBL)
416 #define CONFIG_SYS_RAMBOOT
420 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
421 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
423 #define I2C_MUX_CH_DEFAULT 0x8
424 #define I2C_MUX_CH_VOL_MONITOR 0xa
425 #define I2C_MUX_CH_VSC3316_FS 0xc
426 #define I2C_MUX_CH_VSC3316_BS 0xd
428 /* Voltage monitor on channel 2*/
429 #define I2C_VOL_MONITOR_ADDR 0x40
430 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
431 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
432 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
434 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
435 #ifndef CONFIG_SPL_BUILD
438 #define CONFIG_VOL_MONITOR_IR36021_SET
439 #define CONFIG_VOL_MONITOR_IR36021_READ
440 /* The lowest and highest voltage allowed for T4240RDB */
441 #define VDD_MV_MIN 819
442 #define VDD_MV_MAX 1212
445 * eSPI - Enhanced SPI
449 #ifndef CONFIG_NOBQFMAN
450 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
451 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
452 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
453 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
454 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
455 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
456 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
457 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
458 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
459 CONFIG_SYS_BMAN_CENA_SIZE)
460 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
461 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
462 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
463 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
464 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
465 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
466 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
467 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
468 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
469 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
470 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
471 CONFIG_SYS_QMAN_CENA_SIZE)
472 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
473 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
475 #define CONFIG_SYS_DPAA_FMAN
476 #define CONFIG_SYS_DPAA_PME
477 #define CONFIG_SYS_PMAN
478 #define CONFIG_SYS_DPAA_DCE
479 #define CONFIG_SYS_DPAA_RMAN
480 #define CONFIG_SYS_INTERLAKEN
482 /* Default address of microcode for the Linux Fman driver */
483 #if defined(CONFIG_SPIFLASH)
485 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
486 * env, so we got 0x110000.
488 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
489 #elif defined(CONFIG_SDCARD)
491 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
492 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
493 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
495 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
496 #elif defined(CONFIG_MTD_RAW_NAND)
497 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
499 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
501 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
502 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
503 #endif /* CONFIG_NOBQFMAN */
505 #ifdef CONFIG_SYS_DPAA_FMAN
506 #define SGMII_PHY_ADDR1 0x0
507 #define SGMII_PHY_ADDR2 0x1
508 #define SGMII_PHY_ADDR3 0x2
509 #define SGMII_PHY_ADDR4 0x3
510 #define SGMII_PHY_ADDR5 0x4
511 #define SGMII_PHY_ADDR6 0x5
512 #define SGMII_PHY_ADDR7 0x6
513 #define SGMII_PHY_ADDR8 0x7
514 #define FM1_10GEC1_PHY_ADDR 0x10
515 #define FM1_10GEC2_PHY_ADDR 0x11
516 #define FM2_10GEC1_PHY_ADDR 0x12
517 #define FM2_10GEC2_PHY_ADDR 0x13
518 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
519 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
520 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
521 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
525 #ifdef CONFIG_FSL_SATA_V2
526 #define CONFIG_SYS_SATA_MAX_DEVICE 2
528 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
529 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
531 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
532 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
537 #ifdef CONFIG_FMAN_ENET
538 #define CONFIG_ETHPRIME "FM1@DTSEC1"
544 #define CONFIG_USB_EHCI_FSL
545 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
546 #define CONFIG_HAS_FSL_DR_USB
549 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
550 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
554 #define __USB_PHY_TYPE utmi
557 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
558 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
559 * interleaving. It can be cacheline, page, bank, superbank.
560 * See doc/README.fsl-ddr for details.
562 #ifdef CONFIG_ARCH_T4240
563 #define CTRL_INTLV_PREFERED 3way_4KB
565 #define CTRL_INTLV_PREFERED cacheline
568 #define CONFIG_EXTRA_ENV_SETTINGS \
569 "hwconfig=fsl_ddr:" \
570 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
572 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
574 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
575 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
576 "tftpflash=tftpboot $loadaddr $uboot && " \
577 "protect off $ubootaddr +$filesize && " \
578 "erase $ubootaddr +$filesize && " \
579 "cp.b $loadaddr $ubootaddr $filesize && " \
580 "protect on $ubootaddr +$filesize && " \
581 "cmp.b $loadaddr $ubootaddr $filesize\0" \
582 "consoledev=ttyS0\0" \
583 "ramdiskaddr=2000000\0" \
584 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
585 "fdtaddr=1e00000\0" \
586 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
589 #define CONFIG_HVBOOT \
590 "setenv bootargs config-addr=0x60000000; " \
591 "bootm 0x01000000 - 0x00f00000"
593 #define CONFIG_LINUX \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "setenv ramdiskaddr 0x02000000;" \
597 "setenv fdtaddr 0x00c00000;" \
598 "setenv loadaddr 0x1000000;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
601 #define CONFIG_HDBOOT \
602 "setenv bootargs root=/dev/$bdev rw " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr - $fdtaddr"
608 #define CONFIG_NFSBOOTCOMMAND \
609 "setenv bootargs root=/dev/nfs rw " \
610 "nfsroot=$serverip:$rootpath " \
611 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
612 "console=$consoledev,$baudrate $othbootargs;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr - $fdtaddr"
617 #define CONFIG_RAMBOOTCOMMAND \
618 "setenv bootargs root=/dev/ram rw " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $ramdiskaddr $ramdiskfile;" \
621 "tftp $loadaddr $bootfile;" \
622 "tftp $fdtaddr $fdtfile;" \
623 "bootm $loadaddr $ramdiskaddr $fdtaddr"
625 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
627 #include <asm/fsl_secure_boot.h>
629 #endif /* __CONFIG_H */