Merge tag 'dm-pull-18mar22' of https://source.denx.de/u-boot/custodians/u-boot-dm...
[platform/kernel/u-boot.git] / include / configs / T4240RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2020-2021 NXP
5  */
6
7 /*
8  * T4240 RDB board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include <linux/stringify.h>
14
15 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_PCIE4
17
18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
19
20 #ifdef CONFIG_RAMBOOT_PBL
21 #ifndef CONFIG_SDCARD
22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
24 #else
25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_PAD_TO               0x40000
27 #define CONFIG_SPL_MAX_SIZE             0x28000
28 #define RESET_VECTOR_OFFSET             0x27FFC
29 #define BOOT_PAGE_OFFSET                0x27000
30
31 #ifdef  CONFIG_SDCARD
32 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
33 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
34 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
37 #ifndef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #endif
40 #endif
41
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #endif
47
48 #endif
49 #endif /* CONFIG_RAMBOOT_PBL */
50
51 /* High Level Configuration Options */
52 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
53
54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
55 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
56 #endif
57
58 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
59 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
60 #define CONFIG_PCIE1                    /* PCIE controller 1 */
61 #define CONFIG_PCIE2                    /* PCIE controller 2 */
62 #define CONFIG_PCIE3                    /* PCIE controller 3 */
63
64 /*
65  * These can be toggled for performance analysis, otherwise use default.
66  */
67 #define CONFIG_SYS_CACHE_STASHING
68 #ifdef CONFIG_DDR_ECC
69 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
70 #endif
71
72 #define CONFIG_ENABLE_36BIT_PHYS
73
74 /*
75  *  Config the L3 Cache as L3 SRAM
76  */
77 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
78 #define CONFIG_SYS_L3_SIZE              (512 << 10)
79 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
80 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
81 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
82 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
83 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
84
85 #define CONFIG_SYS_DCSRBAR              0xf0000000
86 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
87
88 /*
89  * DDR Setup
90  */
91 #define CONFIG_VERY_BIG_RAM
92 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
94
95 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
96
97 /*
98  * IFC Definitions
99  */
100 #define CONFIG_SYS_FLASH_BASE   0xe0000000
101 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
102
103 #ifdef CONFIG_SPL_BUILD
104 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
105 #else
106 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
107 #endif
108
109 #define CONFIG_HWCONFIG
110
111 /* define to use L1 as initial stack */
112 #define CONFIG_L1_INIT_RAM
113 #define CONFIG_SYS_INIT_RAM_LOCK
114 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
115 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
116 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
117 /* The assembler doesn't like typecast */
118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
119         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
120           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
121 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
122
123 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
124                                         GENERATED_GBL_DATA_SIZE)
125 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
126
127 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
128
129 /* Serial Port - controlled on board with jumper J8
130  * open - index 2
131  * shorted - index 1
132  */
133 #define CONFIG_SYS_NS16550_SERIAL
134 #define CONFIG_SYS_NS16550_REG_SIZE     1
135 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
136
137 #define CONFIG_SYS_BAUDRATE_TABLE       \
138         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
139
140 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
141 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
142 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
143 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
144
145 /* I2C */
146
147 /*
148  * General PCI
149  * Memory space is mapped 1-1, but I/O space must start from 0.
150  */
151
152 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
153 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
154 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
155 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
156 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
157
158 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
159 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
160 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
161 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
162 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
163
164 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
165 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
166 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
167 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
168 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
169
170 /* controller 4, Base address 203000 */
171 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
172 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
173 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
174
175 #ifdef CONFIG_PCI
176 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
177 #endif  /* CONFIG_PCI */
178
179 /* SATA */
180 #ifdef CONFIG_FSL_SATA_V2
181 #define CONFIG_SATA1
182 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
183 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
184 #define CONFIG_SATA2
185 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
186 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
187
188 #define CONFIG_LBA48
189 #endif
190
191 /*
192  * Environment
193  */
194 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
195 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
196
197 /*
198  * Miscellaneous configurable options
199  */
200
201 /*
202  * For booting Linux, the board info and command line data
203  * have to be in the first 64 MB of memory, since this is
204  * the maximum mapped by the Linux kernel during initialization.
205  */
206 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
207 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
208
209 /*
210  * Environment Configuration
211  */
212 #define CONFIG_ROOTPATH         "/opt/nfsroot"
213 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
214
215 #define HVBOOT                                  \
216         "setenv bootargs config-addr=0x60000000; "      \
217         "bootm 0x01000000 - 0x00f00000"
218
219 /*
220  * DDR Setup
221  */
222 #define CONFIG_SYS_SPD_BUS_NUM  0
223 #define SPD_EEPROM_ADDRESS1     0x52
224 #define SPD_EEPROM_ADDRESS2     0x54
225 #define SPD_EEPROM_ADDRESS3     0x56
226 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
227 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
228
229 /*
230  * IFC Definitions
231  */
232 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
233 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
234                                 + 0x8000000) | \
235                                 CSPR_PORT_SIZE_16 | \
236                                 CSPR_MSEL_NOR | \
237                                 CSPR_V)
238 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
239 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
240                                 CSPR_PORT_SIZE_16 | \
241                                 CSPR_MSEL_NOR | \
242                                 CSPR_V)
243 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
244 /* NOR Flash Timing Params */
245 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
246
247 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
248                                 FTIM0_NOR_TEADC(0x5) | \
249                                 FTIM0_NOR_TEAHC(0x5))
250 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
251                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
252                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
253 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
254                                 FTIM2_NOR_TCH(0x4) | \
255                                 FTIM2_NOR_TWPH(0x0E) | \
256                                 FTIM2_NOR_TWP(0x1c))
257 #define CONFIG_SYS_NOR_FTIM3    0x0
258
259 #define CONFIG_SYS_FLASH_QUIET_TEST
260 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
261
262 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
263 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
265
266 #define CONFIG_SYS_FLASH_EMPTY_INFO
267 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
268                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
269
270 /* NAND Flash on IFC */
271 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
272 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
273 #define CONFIG_SYS_NAND_BASE            0xff800000
274 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
275
276 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
277 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
278                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
279                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
280                                 | CSPR_V)
281 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
282
283 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
284                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
285                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
286                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
287                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
288                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
289                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
290
291 /* ONFI NAND Flash mode0 Timing Params */
292 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
293                                         FTIM0_NAND_TWP(0x18)   | \
294                                         FTIM0_NAND_TWCHT(0x07) | \
295                                         FTIM0_NAND_TWH(0x0a))
296 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
297                                         FTIM1_NAND_TWBE(0x39)  | \
298                                         FTIM1_NAND_TRR(0x0e)   | \
299                                         FTIM1_NAND_TRP(0x18))
300 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
301                                         FTIM2_NAND_TREH(0x0a) | \
302                                         FTIM2_NAND_TWHRE(0x1e))
303 #define CONFIG_SYS_NAND_FTIM3           0x0
304
305 #define CONFIG_SYS_NAND_DDR_LAW         11
306 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
307 #define CONFIG_SYS_MAX_NAND_DEVICE      1
308
309 #if defined(CONFIG_MTD_RAW_NAND)
310 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
311 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
312 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
313 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
314 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
315 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
316 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
317 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
318 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
319 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
320 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
321 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
322 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
323 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
324 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
325 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
326 #else
327 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
328 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
329 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
330 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
331 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
332 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
333 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
334 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
335 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
336 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
337 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
338 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
339 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
340 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
341 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
342 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
343 #endif
344 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
345 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
346 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
347 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
348 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
349 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
350 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
351 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
352
353 /* CPLD on IFC */
354 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
355 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
356 #define CONFIG_SYS_CSPR3_EXT    (0xf)
357 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
358                                 | CSPR_PORT_SIZE_8 \
359                                 | CSPR_MSEL_GPCM \
360                                 | CSPR_V)
361
362 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
363 #define CONFIG_SYS_CSOR3        0x0
364
365 /* CPLD Timing parameters for IFC CS3 */
366 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
367                                         FTIM0_GPCM_TEADC(0x0e) | \
368                                         FTIM0_GPCM_TEAHC(0x0e))
369 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
370                                         FTIM1_GPCM_TRAD(0x1f))
371 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
372                                         FTIM2_GPCM_TCH(0x8) | \
373                                         FTIM2_GPCM_TWP(0x1f))
374 #define CONFIG_SYS_CS3_FTIM3            0x0
375
376 #if defined(CONFIG_RAMBOOT_PBL)
377 #define CONFIG_SYS_RAMBOOT
378 #endif
379
380 /* I2C */
381 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
382 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
383
384 #define I2C_MUX_CH_DEFAULT      0x8
385 #define I2C_MUX_CH_VOL_MONITOR  0xa
386 #define I2C_MUX_CH_VSC3316_FS   0xc
387 #define I2C_MUX_CH_VSC3316_BS   0xd
388
389 /* Voltage monitor on channel 2*/
390 #define I2C_VOL_MONITOR_ADDR            0x40
391 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
392 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
393 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
394
395 /* The lowest and highest voltage allowed for T4240RDB */
396 #define VDD_MV_MIN                      819
397 #define VDD_MV_MAX                      1212
398
399 /*
400  * eSPI - Enhanced SPI
401  */
402
403 /* Qman/Bman */
404 #ifndef CONFIG_NOBQFMAN
405 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
406 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
407 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
408 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
409 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
410 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
411 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
412 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
413 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
414                                         CONFIG_SYS_BMAN_CENA_SIZE)
415 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
416 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
417 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
418 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
419 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
420 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
421 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
422 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
423 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
424 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
425 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
426                                         CONFIG_SYS_QMAN_CENA_SIZE)
427 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
428 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
429
430 #define CONFIG_SYS_DPAA_FMAN
431 #define CONFIG_SYS_DPAA_PME
432 #define CONFIG_SYS_PMAN
433 #define CONFIG_SYS_DPAA_DCE
434 #define CONFIG_SYS_DPAA_RMAN
435 #define CONFIG_SYS_INTERLAKEN
436
437 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
438 #endif /* CONFIG_NOBQFMAN */
439
440 #ifdef CONFIG_SYS_DPAA_FMAN
441 #define SGMII_PHY_ADDR1 0x0
442 #define SGMII_PHY_ADDR2 0x1
443 #define SGMII_PHY_ADDR3 0x2
444 #define SGMII_PHY_ADDR4 0x3
445 #define SGMII_PHY_ADDR5 0x4
446 #define SGMII_PHY_ADDR6 0x5
447 #define SGMII_PHY_ADDR7 0x6
448 #define SGMII_PHY_ADDR8 0x7
449 #define FM1_10GEC1_PHY_ADDR     0x10
450 #define FM1_10GEC2_PHY_ADDR     0x11
451 #define FM2_10GEC1_PHY_ADDR     0x12
452 #define FM2_10GEC2_PHY_ADDR     0x13
453 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
454 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
455 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
456 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
457 #endif
458
459 /* SATA */
460 #ifdef CONFIG_FSL_SATA_V2
461 #define CONFIG_SATA1
462 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
463 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
464 #define CONFIG_SATA2
465 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
466 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
467
468 #define CONFIG_LBA48
469 #endif
470
471 /*
472 * USB
473 */
474 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
475 #define CONFIG_HAS_FSL_DR_USB
476
477 #ifdef CONFIG_MMC
478 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
479 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
480 #endif
481
482
483 #define __USB_PHY_TYPE  utmi
484
485 /*
486  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
487  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
488  * interleaving. It can be cacheline, page, bank, superbank.
489  * See doc/README.fsl-ddr for details.
490  */
491 #ifdef CONFIG_ARCH_T4240
492 #define CTRL_INTLV_PREFERED 3way_4KB
493 #else
494 #define CTRL_INTLV_PREFERED cacheline
495 #endif
496
497 #define CONFIG_EXTRA_ENV_SETTINGS                               \
498         "hwconfig=fsl_ddr:"                                     \
499         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
500         "bank_intlv=auto;"                                      \
501         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
502         "netdev=eth0\0"                                         \
503         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
504         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
505         "tftpflash=tftpboot $loadaddr $uboot && "               \
506         "protect off $ubootaddr +$filesize && "                 \
507         "erase $ubootaddr +$filesize && "                       \
508         "cp.b $loadaddr $ubootaddr $filesize && "               \
509         "protect on $ubootaddr +$filesize && "                  \
510         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
511         "consoledev=ttyS0\0"                                    \
512         "ramdiskaddr=2000000\0"                                 \
513         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
514         "fdtaddr=1e00000\0"                                     \
515         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
516         "bdev=sda3\0"
517
518 #define HVBOOT                                  \
519         "setenv bootargs config-addr=0x60000000; "      \
520         "bootm 0x01000000 - 0x00f00000"
521
522 #include <asm/fsl_secure_boot.h>
523
524 #endif  /* __CONFIG_H */