1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define RESET_VECTOR_OFFSET 0x27FFC
23 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
27 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
30 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
34 #endif /* CONFIG_RAMBOOT_PBL */
36 /* High Level Configuration Options */
38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_SYS_CACHE_STASHING
50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
54 * Config the L3 Cache as L3 SRAM
56 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
57 #define CONFIG_SYS_L3_SIZE (512 << 10)
58 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
60 #define CONFIG_SYS_DCSRBAR 0xf0000000
61 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
66 #define CONFIG_VERY_BIG_RAM
67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
73 #define CONFIG_SYS_FLASH_BASE 0xe0000000
74 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
76 #define CONFIG_HWCONFIG
78 /* define to use L1 as initial stack */
79 #define CONFIG_L1_INIT_RAM
80 #define CONFIG_SYS_INIT_RAM_LOCK
81 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
82 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
83 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
84 /* The assembler doesn't like typecast */
85 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
86 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
87 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
88 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
90 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
92 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
94 /* Serial Port - controlled on board with jumper J8
98 #define CONFIG_SYS_NS16550_SERIAL
99 #define CONFIG_SYS_NS16550_REG_SIZE 1
100 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
102 #define CONFIG_SYS_BAUDRATE_TABLE \
103 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
105 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
106 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
107 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
108 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
114 * Memory space is mapped 1-1, but I/O space must start from 0.
117 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
118 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
119 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
120 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
121 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
123 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
124 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
125 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
126 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
127 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
129 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
130 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
131 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
132 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
133 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
135 /* controller 4, Base address 203000 */
136 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
137 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
138 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
143 #define CONFIG_LOADS_ECHO /* echo on for serial download */
144 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
147 * Miscellaneous configurable options
151 * For booting Linux, the board info and command line data
152 * have to be in the first 64 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization.
155 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
156 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
159 * Environment Configuration
161 #define CONFIG_ROOTPATH "/opt/nfsroot"
162 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
165 "setenv bootargs config-addr=0x60000000; " \
166 "bootm 0x01000000 - 0x00f00000"
171 #define SPD_EEPROM_ADDRESS1 0x52
172 #define SPD_EEPROM_ADDRESS2 0x54
173 #define SPD_EEPROM_ADDRESS3 0x56
174 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
175 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
180 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
181 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
183 CSPR_PORT_SIZE_16 | \
186 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
187 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
188 CSPR_PORT_SIZE_16 | \
191 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
192 /* NOR Flash Timing Params */
193 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
195 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
196 FTIM0_NOR_TEADC(0x5) | \
197 FTIM0_NOR_TEAHC(0x5))
198 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
199 FTIM1_NOR_TRAD_NOR(0x1A) |\
200 FTIM1_NOR_TSEQRAD_NOR(0x13))
201 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
202 FTIM2_NOR_TCH(0x4) | \
203 FTIM2_NOR_TWPH(0x0E) | \
205 #define CONFIG_SYS_NOR_FTIM3 0x0
207 #define CONFIG_SYS_FLASH_QUIET_TEST
208 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
210 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
214 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
216 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
218 /* NAND Flash on IFC */
219 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
220 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
221 #define CONFIG_SYS_NAND_BASE 0xff800000
222 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
224 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
227 | CSPR_MSEL_NAND /* MSEL = NAND */ \
229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
234 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
236 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
237 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
239 /* ONFI NAND Flash mode0 Timing Params */
240 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
241 FTIM0_NAND_TWP(0x18) | \
242 FTIM0_NAND_TWCHT(0x07) | \
243 FTIM0_NAND_TWH(0x0a))
244 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
245 FTIM1_NAND_TWBE(0x39) | \
246 FTIM1_NAND_TRR(0x0e) | \
247 FTIM1_NAND_TRP(0x18))
248 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
249 FTIM2_NAND_TREH(0x0a) | \
250 FTIM2_NAND_TWHRE(0x1e))
251 #define CONFIG_SYS_NAND_FTIM3 0x0
253 #define CONFIG_SYS_NAND_DDR_LAW 11
254 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
255 #define CONFIG_SYS_MAX_NAND_DEVICE 1
257 #if defined(CONFIG_MTD_RAW_NAND)
258 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
259 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
260 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
261 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
262 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
263 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
264 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
265 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
266 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
267 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
268 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
269 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
270 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
271 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
272 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
273 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
275 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
276 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
277 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
278 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
279 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
280 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
281 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
282 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
283 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
284 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
285 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
286 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
287 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
288 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
289 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
290 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
292 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
293 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
294 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
302 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
303 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
304 #define CONFIG_SYS_CSPR3_EXT (0xf)
305 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
310 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
311 #define CONFIG_SYS_CSOR3 0x0
313 /* CPLD Timing parameters for IFC CS3 */
314 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
315 FTIM0_GPCM_TEADC(0x0e) | \
316 FTIM0_GPCM_TEAHC(0x0e))
317 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
318 FTIM1_GPCM_TRAD(0x1f))
319 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
320 FTIM2_GPCM_TCH(0x8) | \
321 FTIM2_GPCM_TWP(0x1f))
322 #define CONFIG_SYS_CS3_FTIM3 0x0
325 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
326 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
328 #define I2C_MUX_CH_DEFAULT 0x8
329 #define I2C_MUX_CH_VOL_MONITOR 0xa
330 #define I2C_MUX_CH_VSC3316_FS 0xc
331 #define I2C_MUX_CH_VSC3316_BS 0xd
333 /* Voltage monitor on channel 2*/
334 #define I2C_VOL_MONITOR_ADDR 0x40
335 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
336 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
337 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
339 /* The lowest and highest voltage allowed for T4240RDB */
340 #define VDD_MV_MIN 819
341 #define VDD_MV_MAX 1212
344 * eSPI - Enhanced SPI
348 #ifndef CONFIG_NOBQFMAN
349 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
350 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
351 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
352 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
353 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
354 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
355 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
356 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
357 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
358 CONFIG_SYS_BMAN_CENA_SIZE)
359 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
360 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
361 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
362 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
363 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
364 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
365 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
366 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
367 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
368 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
369 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
370 CONFIG_SYS_QMAN_CENA_SIZE)
371 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
372 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
374 #define CONFIG_SYS_DPAA_FMAN
375 #define CONFIG_SYS_DPAA_PME
376 #define CONFIG_SYS_PMAN
377 #define CONFIG_SYS_DPAA_DCE
378 #define CONFIG_SYS_DPAA_RMAN
379 #define CONFIG_SYS_INTERLAKEN
381 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
382 #endif /* CONFIG_NOBQFMAN */
384 #ifdef CONFIG_SYS_DPAA_FMAN
385 #define SGMII_PHY_ADDR1 0x0
386 #define SGMII_PHY_ADDR2 0x1
387 #define SGMII_PHY_ADDR3 0x2
388 #define SGMII_PHY_ADDR4 0x3
389 #define SGMII_PHY_ADDR5 0x4
390 #define SGMII_PHY_ADDR6 0x5
391 #define SGMII_PHY_ADDR7 0x6
392 #define SGMII_PHY_ADDR8 0x7
393 #define FM1_10GEC1_PHY_ADDR 0x10
394 #define FM1_10GEC2_PHY_ADDR 0x11
395 #define FM2_10GEC1_PHY_ADDR 0x12
396 #define FM2_10GEC2_PHY_ADDR 0x13
397 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
398 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
399 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
400 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
408 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
409 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
413 #define __USB_PHY_TYPE utmi
416 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
417 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
418 * interleaving. It can be cacheline, page, bank, superbank.
419 * See doc/README.fsl-ddr for details.
421 #ifdef CONFIG_ARCH_T4240
422 #define CTRL_INTLV_PREFERED 3way_4KB
424 #define CTRL_INTLV_PREFERED cacheline
427 #define CONFIG_EXTRA_ENV_SETTINGS \
428 "hwconfig=fsl_ddr:" \
429 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
431 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
433 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
434 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
435 "tftpflash=tftpboot $loadaddr $uboot && " \
436 "protect off $ubootaddr +$filesize && " \
437 "erase $ubootaddr +$filesize && " \
438 "cp.b $loadaddr $ubootaddr $filesize && " \
439 "protect on $ubootaddr +$filesize && " \
440 "cmp.b $loadaddr $ubootaddr $filesize\0" \
441 "consoledev=ttyS0\0" \
442 "ramdiskaddr=2000000\0" \
443 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
444 "fdtaddr=1e00000\0" \
445 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
449 "setenv bootargs config-addr=0x60000000; " \
450 "bootm 0x01000000 - 0x00f00000"
452 #include <asm/fsl_secure_boot.h>
454 #endif /* __CONFIG_H */