include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifndef CONFIG_SDCARD
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #else
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24
  25 #ifdef  CONFIG_SDCARD
  26 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  27 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  28 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  29 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  30 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  31 #endif
  32
  33 #endif
  34 #endif /* CONFIG_RAMBOOT_PBL */
  35
  36 /* High Level Configuration Options */
  37
  38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  40 #endif
  41
  42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  43
  44 /*
  45  * These can be toggled for performance analysis, otherwise use default.
  46  */
  47 #ifdef CONFIG_DDR_ECC
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #endif
  50
  51 /*
  52  *  Config the L3 Cache as L3 SRAM
  53  */
  54 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  55 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  56 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  57
  58 #define CONFIG_SYS_DCSRBAR              0xf0000000
  59 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_VERY_BIG_RAM
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  66 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  67
  68 /*
  69  * IFC Definitions
  70  */
  71 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  72 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  73
  74 #define CONFIG_HWCONFIG
  75
  76 /* define to use L1 as initial stack */
  77 #define CONFIG_L1_INIT_RAM
  78 #define CONFIG_SYS_INIT_RAM_LOCK
  79 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
  80 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
  81 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
  82 /* The assembler doesn't like typecast */
  83 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  84         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  85           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  86 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
  87
  88 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  89
  90 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  91
  92 /* Serial Port - controlled on board with jumper J8
  93  * open - index 2
  94  * shorted - index 1
  95  */
  96 #define CONFIG_SYS_NS16550_SERIAL
  97 #define CONFIG_SYS_NS16550_REG_SIZE     1
  98 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
  99
 100 #define CONFIG_SYS_BAUDRATE_TABLE       \
 101         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 102
 103 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 104 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 105 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 106 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 107
 108 /* I2C */
 109
 110 /*
 111  * General PCI
 112  * Memory space is mapped 1-1, but I/O space must start from 0.
 113  */
 114
 115 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 116 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 117 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 118 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 119 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 120
 121 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 122 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 123 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 124 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 125 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 126
 127 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 128 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 129 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 130 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 131 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 132
 133 /* controller 4, Base address 203000 */
 134 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 135 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 136 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 137
 138 /*
 139  * Environment
 140  */
 141 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 142 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 143
 144 /*
 145  * Miscellaneous configurable options
 146  */
 147
 148 /*
 149  * For booting Linux, the board info and command line data
 150  * have to be in the first 64 MB of memory, since this is
 151  * the maximum mapped by the Linux kernel during initialization.
 152  */
 153 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 154
 155 /*
 156  * Environment Configuration
 157  */
 158 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 159 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 160
 161 #define HVBOOT                                  \
 162         "setenv bootargs config-addr=0x60000000; "      \
 163         "bootm 0x01000000 - 0x00f00000"
 164
 165 /*
 166  * DDR Setup
 167  */
 168 #define SPD_EEPROM_ADDRESS1     0x52
 169 #define SPD_EEPROM_ADDRESS2     0x54
 170 #define SPD_EEPROM_ADDRESS3     0x56
 171 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 172 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 173
 174 /*
 175  * IFC Definitions
 176  */
 177 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 178 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 179                                 + 0x8000000) | \
 180                                 CSPR_PORT_SIZE_16 | \
 181                                 CSPR_MSEL_NOR | \
 182                                 CSPR_V)
 183 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 184 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 185                                 CSPR_PORT_SIZE_16 | \
 186                                 CSPR_MSEL_NOR | \
 187                                 CSPR_V)
 188 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 189 /* NOR Flash Timing Params */
 190 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 191
 192 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 193                                 FTIM0_NOR_TEADC(0x5) | \
 194                                 FTIM0_NOR_TEAHC(0x5))
 195 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 196                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 197                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 198 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 199                                 FTIM2_NOR_TCH(0x4) | \
 200                                 FTIM2_NOR_TWPH(0x0E) | \
 201                                 FTIM2_NOR_TWP(0x1c))
 202 #define CONFIG_SYS_NOR_FTIM3    0x0
 203
 204 #define CONFIG_SYS_FLASH_QUIET_TEST
 205 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 210
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO
 212 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 213                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 214
 215 /* NAND Flash on IFC */
 216 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 217 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 218 #define CONFIG_SYS_NAND_BASE            0xff800000
 219 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 220
 221 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 222 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 223                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 224                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 225                                 | CSPR_V)
 226 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 227
 228 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 229                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 230                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 231                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 232                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 233                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 234                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 235
 236 /* ONFI NAND Flash mode0 Timing Params */
 237 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 238                                         FTIM0_NAND_TWP(0x18)   | \
 239                                         FTIM0_NAND_TWCHT(0x07) | \
 240                                         FTIM0_NAND_TWH(0x0a))
 241 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 242                                         FTIM1_NAND_TWBE(0x39)  | \
 243                                         FTIM1_NAND_TRR(0x0e)   | \
 244                                         FTIM1_NAND_TRP(0x18))
 245 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 246                                         FTIM2_NAND_TREH(0x0a) | \
 247                                         FTIM2_NAND_TWHRE(0x1e))
 248 #define CONFIG_SYS_NAND_FTIM3           0x0
 249
 250 #define CONFIG_SYS_NAND_DDR_LAW         11
 251 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 252 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 253
 254 #if defined(CONFIG_MTD_RAW_NAND)
 255 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 256 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 257 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 258 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 259 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 260 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 261 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 262 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 263 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 264 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 265 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 266 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 267 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 268 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 269 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 270 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 271 #else
 272 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 273 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 274 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 275 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 276 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 277 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 278 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 279 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 280 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 281 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 282 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 283 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 284 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 285 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 286 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 287 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 288 #endif
 289 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 290 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 291 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 292 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 293 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 294 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 295 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 296 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 297
 298 /* CPLD on IFC */
 299 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 300 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 301 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 302 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 303                                 | CSPR_PORT_SIZE_8 \
 304                                 | CSPR_MSEL_GPCM \
 305                                 | CSPR_V)
 306
 307 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 308 #define CONFIG_SYS_CSOR3        0x0
 309
 310 /* CPLD Timing parameters for IFC CS3 */
 311 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 312                                         FTIM0_GPCM_TEADC(0x0e) | \
 313                                         FTIM0_GPCM_TEAHC(0x0e))
 314 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 315                                         FTIM1_GPCM_TRAD(0x1f))
 316 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 317                                         FTIM2_GPCM_TCH(0x8) | \
 318                                         FTIM2_GPCM_TWP(0x1f))
 319 #define CONFIG_SYS_CS3_FTIM3            0x0
 320
 321 /* I2C */
 322 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 323 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 324
 325 #define I2C_MUX_CH_DEFAULT      0x8
 326 #define I2C_MUX_CH_VOL_MONITOR  0xa
 327 #define I2C_MUX_CH_VSC3316_FS   0xc
 328 #define I2C_MUX_CH_VSC3316_BS   0xd
 329
 330 /* Voltage monitor on channel 2*/
 331 #define I2C_VOL_MONITOR_ADDR            0x40
 332 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 333 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 334 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 335
 336 /* The lowest and highest voltage allowed for T4240RDB */
 337 #define VDD_MV_MIN                      819
 338 #define VDD_MV_MAX                      1212
 339
 340 /*
 341  * eSPI - Enhanced SPI
 342  */
 343
 344 /* Qman/Bman */
 345 #ifndef CONFIG_NOBQFMAN
 346 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 347 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 348 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 349 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 350 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 351 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 352 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 353 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 354 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 355                                         CONFIG_SYS_BMAN_CENA_SIZE)
 356 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 357 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 358 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 359 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 360 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 361 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 362 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 363 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 364 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 365 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 366 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 367                                         CONFIG_SYS_QMAN_CENA_SIZE)
 368 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 370
 371 #define CONFIG_SYS_DPAA_FMAN
 372 #define CONFIG_SYS_DPAA_PME
 373 #define CONFIG_SYS_PMAN
 374 #define CONFIG_SYS_DPAA_DCE
 375 #define CONFIG_SYS_DPAA_RMAN
 376 #define CONFIG_SYS_INTERLAKEN
 377
 378 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 379 #endif /* CONFIG_NOBQFMAN */
 380
 381 #ifdef CONFIG_SYS_DPAA_FMAN
 382 #define SGMII_PHY_ADDR1 0x0
 383 #define SGMII_PHY_ADDR2 0x1
 384 #define SGMII_PHY_ADDR3 0x2
 385 #define SGMII_PHY_ADDR4 0x3
 386 #define SGMII_PHY_ADDR5 0x4
 387 #define SGMII_PHY_ADDR6 0x5
 388 #define SGMII_PHY_ADDR7 0x6
 389 #define SGMII_PHY_ADDR8 0x7
 390 #define FM1_10GEC1_PHY_ADDR     0x10
 391 #define FM1_10GEC2_PHY_ADDR     0x11
 392 #define FM2_10GEC1_PHY_ADDR     0x12
 393 #define FM2_10GEC2_PHY_ADDR     0x13
 394 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 395 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 396 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 397 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 398 #endif
 399
 400 /*
 401 * USB
 402 */
 403
 404 #ifdef CONFIG_MMC
 405 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 406 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 407 #endif
 408
 409
 410 #define __USB_PHY_TYPE  utmi
 411
 412 /*
 413  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 414  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 415  * interleaving. It can be cacheline, page, bank, superbank.
 416  * See doc/README.fsl-ddr for details.
 417  */
 418 #ifdef CONFIG_ARCH_T4240
 419 #define CTRL_INTLV_PREFERED 3way_4KB
 420 #else
 421 #define CTRL_INTLV_PREFERED cacheline
 422 #endif
 423
 424 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 425         "hwconfig=fsl_ddr:"                                     \
 426         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 427         "bank_intlv=auto;"                                      \
 428         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 429         "netdev=eth0\0"                                         \
 430         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 431         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 432         "tftpflash=tftpboot $loadaddr $uboot && "               \
 433         "protect off $ubootaddr +$filesize && "                 \
 434         "erase $ubootaddr +$filesize && "                       \
 435         "cp.b $loadaddr $ubootaddr $filesize && "               \
 436         "protect on $ubootaddr +$filesize && "                  \
 437         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 438         "consoledev=ttyS0\0"                                    \
 439         "ramdiskaddr=2000000\0"                                 \
 440         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 441         "fdtaddr=1e00000\0"                                     \
 442         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 443         "bdev=sda3\0"
 444
 445 #define HVBOOT                                  \
 446         "setenv bootargs config-addr=0x60000000; "      \
 447         "bootm 0x01000000 - 0x00f00000"
 448
 449 #include <asm/fsl_secure_boot.h>
 450
 451 #endif  /* __CONFIG_H */