1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #define RESET_VECTOR_OFFSET 0x27FFC
22 #define BOOT_PAGE_OFFSET 0x27000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
26 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
27 #define CFG_SYS_MMC_U_BOOT_DST 0x00200000
28 #define CFG_SYS_MMC_U_BOOT_START 0x00200000
29 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
33 #endif /* CONFIG_RAMBOOT_PBL */
35 /* High Level Configuration Options */
37 #ifndef CONFIG_RESET_VECTOR_ADDRESS
38 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
41 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
44 * These can be toggled for performance analysis, otherwise use default.
47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
51 * Config the L3 Cache as L3 SRAM
53 #define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
54 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
56 #define CFG_SYS_DCSRBAR 0xf0000000
57 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
62 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000
63 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
68 #define CFG_SYS_FLASH_BASE 0xe0000000
69 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
71 /* define to use L1 as initial stack */
72 #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
73 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
74 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
75 /* The assembler doesn't like typecast */
76 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
77 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
78 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
79 #define CFG_SYS_INIT_RAM_SIZE 0x00004000
81 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83 /* Serial Port - controlled on board with jumper J8
87 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
89 #define CFG_SYS_BAUDRATE_TABLE \
90 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
92 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
93 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
94 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
95 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
101 * Memory space is mapped 1-1, but I/O space must start from 0.
104 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
105 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
106 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
107 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
108 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
110 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
111 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
112 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
113 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
114 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
116 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
117 #define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
118 #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
120 /* controller 4, Base address 203000 */
121 #define CFG_SYS_PCIE4_MEM_BUS 0xe0000000
122 #define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
125 * Miscellaneous configurable options
129 * For booting Linux, the board info and command line data
130 * have to be in the first 64 MB of memory, since this is
131 * the maximum mapped by the Linux kernel during initialization.
133 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
136 * Environment Configuration
140 "setenv bootargs config-addr=0x60000000; " \
141 "bootm 0x01000000 - 0x00f00000"
146 #define SPD_EEPROM_ADDRESS1 0x52
147 #define SPD_EEPROM_ADDRESS2 0x54
148 #define SPD_EEPROM_ADDRESS3 0x56
149 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
150 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
155 #define CFG_SYS_NOR0_CSPR_EXT (0xf)
156 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
158 CSPR_PORT_SIZE_16 | \
161 #define CFG_SYS_NOR1_CSPR_EXT (0xf)
162 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
163 CSPR_PORT_SIZE_16 | \
166 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
167 /* NOR Flash Timing Params */
168 #define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
170 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
171 FTIM0_NOR_TEADC(0x5) | \
172 FTIM0_NOR_TEAHC(0x5))
173 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
174 FTIM1_NOR_TRAD_NOR(0x1A) |\
175 FTIM1_NOR_TSEQRAD_NOR(0x13))
176 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
177 FTIM2_NOR_TCH(0x4) | \
178 FTIM2_NOR_TWPH(0x0E) | \
180 #define CFG_SYS_NOR_FTIM3 0x0
182 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
183 + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
185 /* NAND Flash on IFC */
186 #define CFG_SYS_NAND_BASE 0xff800000
187 #define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
189 #define CFG_SYS_NAND_CSPR_EXT (0xf)
190 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
191 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
192 | CSPR_MSEL_NAND /* MSEL = NAND */ \
194 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
196 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
197 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
198 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
199 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
200 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
201 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
202 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
204 /* ONFI NAND Flash mode0 Timing Params */
205 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
206 FTIM0_NAND_TWP(0x18) | \
207 FTIM0_NAND_TWCHT(0x07) | \
208 FTIM0_NAND_TWH(0x0a))
209 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
210 FTIM1_NAND_TWBE(0x39) | \
211 FTIM1_NAND_TRR(0x0e) | \
212 FTIM1_NAND_TRP(0x18))
213 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
214 FTIM2_NAND_TREH(0x0a) | \
215 FTIM2_NAND_TWHRE(0x1e))
216 #define CFG_SYS_NAND_FTIM3 0x0
218 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
220 #if defined(CONFIG_MTD_RAW_NAND)
221 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
222 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
223 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
224 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
225 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
226 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
227 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
228 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
229 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
230 #define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR
231 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
232 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
233 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
234 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
235 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
236 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
238 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
239 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
240 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
241 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
242 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
243 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
244 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
245 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
246 #define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
247 #define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
248 #define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
249 #define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
250 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
251 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
252 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
253 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
255 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
256 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
257 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
258 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
259 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
260 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
261 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
262 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
265 #define CFG_SYS_CPLD_BASE 0xffdf0000
266 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
267 #define CFG_SYS_CSPR3_EXT (0xf)
268 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
273 #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
274 #define CFG_SYS_CSOR3 0x0
276 /* CPLD Timing parameters for IFC CS3 */
277 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
278 FTIM0_GPCM_TEADC(0x0e) | \
279 FTIM0_GPCM_TEAHC(0x0e))
280 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
281 FTIM1_GPCM_TRAD(0x1f))
282 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
283 FTIM2_GPCM_TCH(0x8) | \
284 FTIM2_GPCM_TWP(0x1f))
285 #define CFG_SYS_CS3_FTIM3 0x0
288 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
289 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
291 #define I2C_MUX_CH_DEFAULT 0x8
292 #define I2C_MUX_CH_VOL_MONITOR 0xa
293 #define I2C_MUX_CH_VSC3316_FS 0xc
294 #define I2C_MUX_CH_VSC3316_BS 0xd
296 /* Voltage monitor on channel 2*/
297 #define I2C_VOL_MONITOR_ADDR 0x40
298 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
299 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
300 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
302 /* The lowest and highest voltage allowed for T4240RDB */
303 #define VDD_MV_MIN 819
304 #define VDD_MV_MAX 1212
307 * eSPI - Enhanced SPI
311 #ifndef CONFIG_NOBQFMAN
312 #define CFG_SYS_BMAN_NUM_PORTALS 50
313 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000
314 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
315 #define CFG_SYS_BMAN_MEM_SIZE 0x02000000
316 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
317 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
318 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
319 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
320 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
321 CFG_SYS_BMAN_CENA_SIZE)
322 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
323 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
324 #define CFG_SYS_QMAN_NUM_PORTALS 50
325 #define CFG_SYS_QMAN_MEM_BASE 0xf6000000
326 #define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
327 #define CFG_SYS_QMAN_MEM_SIZE 0x02000000
328 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
329 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
330 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
331 CFG_SYS_QMAN_CENA_SIZE)
332 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
333 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
334 #endif /* CONFIG_NOBQFMAN */
336 #ifdef CONFIG_SYS_DPAA_FMAN
337 #define SGMII_PHY_ADDR1 0x0
338 #define SGMII_PHY_ADDR2 0x1
339 #define SGMII_PHY_ADDR3 0x2
340 #define SGMII_PHY_ADDR4 0x3
341 #define SGMII_PHY_ADDR5 0x4
342 #define SGMII_PHY_ADDR6 0x5
343 #define SGMII_PHY_ADDR7 0x6
344 #define SGMII_PHY_ADDR8 0x7
345 #define FM1_10GEC1_PHY_ADDR 0x10
346 #define FM1_10GEC2_PHY_ADDR 0x11
347 #define FM2_10GEC1_PHY_ADDR 0x12
348 #define FM2_10GEC2_PHY_ADDR 0x13
349 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
350 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
351 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
352 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
360 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
364 #define __USB_PHY_TYPE utmi
367 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
368 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
369 * interleaving. It can be cacheline, page, bank, superbank.
370 * See doc/README.fsl-ddr for details.
372 #ifdef CONFIG_ARCH_T4240
373 #define CTRL_INTLV_PREFERED 3way_4KB
375 #define CTRL_INTLV_PREFERED cacheline
378 #define CONFIG_EXTRA_ENV_SETTINGS \
379 "hwconfig=fsl_ddr:" \
380 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
382 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
384 "uboot=" CONFIG_UBOOTPATH "\0" \
385 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
386 "tftpflash=tftpboot $loadaddr $uboot && " \
387 "protect off $ubootaddr +$filesize && " \
388 "erase $ubootaddr +$filesize && " \
389 "cp.b $loadaddr $ubootaddr $filesize && " \
390 "protect on $ubootaddr +$filesize && " \
391 "cmp.b $loadaddr $ubootaddr $filesize\0" \
392 "consoledev=ttyS0\0" \
393 "ramdiskaddr=2000000\0" \
394 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
395 "fdtaddr=1e00000\0" \
396 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
400 "setenv bootargs config-addr=0x60000000; " \
401 "bootm 0x01000000 - 0x00f00000"
403 #include <asm/fsl_secure_boot.h>
405 #endif /* __CONFIG_H */