include/configs/T4240RDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SYS_TEXT_BASE            0x00201000
  27 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32
  33 #ifdef  CONFIG_SDCARD
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  35 #define CONFIG_SPL_MMC_MINIMAL
  36 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  37 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  38 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  39 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  40 #ifndef CONFIG_SPL_BUILD
  41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42 #endif
  43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  45 #define CONFIG_SPL_MMC_BOOT
  46 #endif
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_SKIP_RELOCATE
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  52 #define CONFIG_SYS_NO_FLASH
  53 #endif
  54
  55 #endif
  56 #endif /* CONFIG_RAMBOOT_PBL */
  57
  58 #define CONFIG_DDR_ECC
  59
  60 #define CONFIG_CMD_REGINFO
  61
  62 /* High Level Configuration Options */
  63 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  64 #define CONFIG_MP                       /* support multiple processors */
  65
  66 #ifndef CONFIG_SYS_TEXT_BASE
  67 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  68 #endif
  69
  70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  72 #endif
  73
  74 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  75 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  76 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  77 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  78 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  79 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  80 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  81 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  82 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  83
  84 #define CONFIG_ENV_OVERWRITE
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #define CONFIG_BTB                      /* toggle branch predition */
  91 #ifdef CONFIG_DDR_ECC
  92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  93 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  94 #endif
  95
  96 #define CONFIG_ENABLE_36BIT_PHYS
  97
  98 #define CONFIG_ADDR_MAP
  99 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 100
 101 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 102 #define CONFIG_SYS_MEMTEST_END          0x00400000
 103 #define CONFIG_SYS_ALT_MEMTEST
 104 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 105
 106 /*
 107  *  Config the L3 Cache as L3 SRAM
 108  */
 109 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 110 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 111 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 112 #ifdef CONFIG_RAMBOOT_PBL
 113 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 114 #endif
 115 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 116 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 117 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 118 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 119
 120 #define CONFIG_SYS_DCSRBAR              0xf0000000
 121 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_VERY_BIG_RAM
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 129
 130 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 131 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 132 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 133
 134 #define CONFIG_DDR_SPD
 135
 136 /*
 137  * IFC Definitions
 138  */
 139 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 140 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 141
 142 #ifdef CONFIG_SPL_BUILD
 143 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 144 #else
 145 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 146 #endif
 147
 148 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 149 #define CONFIG_MISC_INIT_R
 150
 151 #define CONFIG_HWCONFIG
 152
 153 /* define to use L1 as initial stack */
 154 #define CONFIG_L1_INIT_RAM
 155 #define CONFIG_SYS_INIT_RAM_LOCK
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 159 /* The assembler doesn't like typecast */
 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 161         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 162           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 163 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 164
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 166                                         GENERATED_GBL_DATA_SIZE)
 167 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 168
 169 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 170 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 171
 172 /* Serial Port - controlled on board with jumper J8
 173  * open - index 2
 174  * shorted - index 1
 175  */
 176 #define CONFIG_CONS_INDEX       1
 177 #define CONFIG_SYS_NS16550_SERIAL
 178 #define CONFIG_SYS_NS16550_REG_SIZE     1
 179 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 180
 181 #define CONFIG_SYS_BAUDRATE_TABLE       \
 182         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 183
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 186 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 187 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 188
 189 /* I2C */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_I2C_FSL
 192 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 193 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 194 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 195 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 196
 197 /*
 198  * General PCI
 199  * Memory space is mapped 1-1, but I/O space must start from 0.
 200  */
 201
 202 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 203 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 204 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 205 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 206 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 207 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 208 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 209 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 210 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 211
 212 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 213 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 214 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 215 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 216 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 217 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 218 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 219 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 220 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 221
 222 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 223 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 224 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 225 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 226 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 227 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 228 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 229 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 230 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 231
 232 /* controller 4, Base address 203000 */
 233 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 234 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 235 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 236 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 237 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 238 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 239
 240 #ifdef CONFIG_PCI
 241 #define CONFIG_PCI_INDIRECT_BRIDGE
 242
 243 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 244 #define CONFIG_DOS_PARTITION
 245 #endif  /* CONFIG_PCI */
 246
 247 /* SATA */
 248 #ifdef CONFIG_FSL_SATA_V2
 249 #define CONFIG_LIBATA
 250 #define CONFIG_FSL_SATA
 251
 252 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 253 #define CONFIG_SATA1
 254 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 255 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 256 #define CONFIG_SATA2
 257 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 258 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 259
 260 #define CONFIG_LBA48
 261 #define CONFIG_CMD_SATA
 262 #define CONFIG_DOS_PARTITION
 263 #endif
 264
 265 #ifdef CONFIG_FMAN_ENET
 266 #define CONFIG_MII              /* MII PHY management */
 267 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 268 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 269 #endif
 270
 271 /*
 272  * Environment
 273  */
 274 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 275 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 276
 277 /*
 278  * Command line configuration.
 279  */
 280 #define CONFIG_CMD_ERRATA
 281 #define CONFIG_CMD_IRQ
 282
 283 #ifdef CONFIG_PCI
 284 #define CONFIG_CMD_PCI
 285 #endif
 286
 287 /*
 288  * Miscellaneous configurable options
 289  */
 290 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 291 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 292 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 293 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 294 #ifdef CONFIG_CMD_KGDB
 295 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 296 #else
 297 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 298 #endif
 299 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 300 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 301 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 302
 303 /*
 304  * For booting Linux, the board info and command line data
 305  * have to be in the first 64 MB of memory, since this is
 306  * the maximum mapped by the Linux kernel during initialization.
 307  */
 308 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 309 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 310
 311 #ifdef CONFIG_CMD_KGDB
 312 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 313 #endif
 314
 315 /*
 316  * Environment Configuration
 317  */
 318 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 319 #define CONFIG_BOOTFILE         "uImage"
 320 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 321
 322 /* default location for tftp and bootm */
 323 #define CONFIG_LOADADDR         1000000
 324
 325 #define CONFIG_BAUDRATE 115200
 326
 327 #define CONFIG_HVBOOT                                   \
 328         "setenv bootargs config-addr=0x60000000; "      \
 329         "bootm 0x01000000 - 0x00f00000"
 330
 331 #ifdef CONFIG_SYS_NO_FLASH
 332 #ifndef CONFIG_RAMBOOT_PBL
 333 #define CONFIG_ENV_IS_NOWHERE
 334 #endif
 335 #else
 336 #define CONFIG_FLASH_CFI_DRIVER
 337 #define CONFIG_SYS_FLASH_CFI
 338 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 339 #endif
 340
 341 #if defined(CONFIG_SPIFLASH)
 342 #define CONFIG_SYS_EXTRA_ENV_RELOC
 343 #define CONFIG_ENV_IS_IN_SPI_FLASH
 344 #define CONFIG_ENV_SPI_BUS              0
 345 #define CONFIG_ENV_SPI_CS               0
 346 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 347 #define CONFIG_ENV_SPI_MODE             0
 348 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 349 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 350 #define CONFIG_ENV_SECT_SIZE            0x10000
 351 #elif defined(CONFIG_SDCARD)
 352 #define CONFIG_SYS_EXTRA_ENV_RELOC
 353 #define CONFIG_ENV_IS_IN_MMC
 354 #define CONFIG_SYS_MMC_ENV_DEV          0
 355 #define CONFIG_ENV_SIZE                 0x2000
 356 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 357 #elif defined(CONFIG_NAND)
 358 #define CONFIG_SYS_EXTRA_ENV_RELOC
 359 #define CONFIG_ENV_IS_IN_NAND
 360 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 361 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 362 #elif defined(CONFIG_ENV_IS_NOWHERE)
 363 #define CONFIG_ENV_SIZE         0x2000
 364 #else
 365 #define CONFIG_ENV_IS_IN_FLASH
 366 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 367 #define CONFIG_ENV_SIZE         0x2000
 368 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 369 #endif
 370
 371 #define CONFIG_SYS_CLK_FREQ     66666666
 372 #define CONFIG_DDR_CLK_FREQ     133333333
 373
 374 #ifndef __ASSEMBLY__
 375 unsigned long get_board_sys_clk(void);
 376 unsigned long get_board_ddr_clk(void);
 377 #endif
 378
 379 /*
 380  * DDR Setup
 381  */
 382 #define CONFIG_SYS_SPD_BUS_NUM  0
 383 #define SPD_EEPROM_ADDRESS1     0x52
 384 #define SPD_EEPROM_ADDRESS2     0x54
 385 #define SPD_EEPROM_ADDRESS3     0x56
 386 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 387 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 388
 389 /*
 390  * IFC Definitions
 391  */
 392 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 393 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 394                                 + 0x8000000) | \
 395                                 CSPR_PORT_SIZE_16 | \
 396                                 CSPR_MSEL_NOR | \
 397                                 CSPR_V)
 398 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 399 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 400                                 CSPR_PORT_SIZE_16 | \
 401                                 CSPR_MSEL_NOR | \
 402                                 CSPR_V)
 403 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 404 /* NOR Flash Timing Params */
 405 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 406
 407 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 408                                 FTIM0_NOR_TEADC(0x5) | \
 409                                 FTIM0_NOR_TEAHC(0x5))
 410 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 411                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 412                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 413 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 414                                 FTIM2_NOR_TCH(0x4) | \
 415                                 FTIM2_NOR_TWPH(0x0E) | \
 416                                 FTIM2_NOR_TWP(0x1c))
 417 #define CONFIG_SYS_NOR_FTIM3    0x0
 418
 419 #define CONFIG_SYS_FLASH_QUIET_TEST
 420 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 421
 422 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 423 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 424 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 425 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 426
 427 #define CONFIG_SYS_FLASH_EMPTY_INFO
 428 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 429                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 430
 431 /* NAND Flash on IFC */
 432 #define CONFIG_NAND_FSL_IFC
 433 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 434 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 435 #define CONFIG_SYS_NAND_BASE            0xff800000
 436 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 437
 438 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 439 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 440                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 441                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 442                                 | CSPR_V)
 443 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 444
 445 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 446                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 447                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 448                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 449                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 450                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 451                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 452
 453 #define CONFIG_SYS_NAND_ONFI_DETECTION
 454
 455 /* ONFI NAND Flash mode0 Timing Params */
 456 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 457                                         FTIM0_NAND_TWP(0x18)   | \
 458                                         FTIM0_NAND_TWCHT(0x07) | \
 459                                         FTIM0_NAND_TWH(0x0a))
 460 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 461                                         FTIM1_NAND_TWBE(0x39)  | \
 462                                         FTIM1_NAND_TRR(0x0e)   | \
 463                                         FTIM1_NAND_TRP(0x18))
 464 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 465                                         FTIM2_NAND_TREH(0x0a) | \
 466                                         FTIM2_NAND_TWHRE(0x1e))
 467 #define CONFIG_SYS_NAND_FTIM3           0x0
 468
 469 #define CONFIG_SYS_NAND_DDR_LAW         11
 470 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 471 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 472 #define CONFIG_CMD_NAND
 473
 474 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 475
 476 #if defined(CONFIG_NAND)
 477 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 478 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 479 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 480 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 481 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 482 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 483 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 484 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 485 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 486 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 487 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 488 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 489 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 490 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 491 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 492 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 493 #else
 494 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 495 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 496 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 497 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 498 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 499 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 500 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 501 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 502 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 503 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 504 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 505 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 506 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 507 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 508 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 509 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 510 #endif
 511 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 512 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 513 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 514 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 515 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 516 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 517 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 518 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 519
 520 /* CPLD on IFC */
 521 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 522 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 523 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 524 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 525                                 | CSPR_PORT_SIZE_8 \
 526                                 | CSPR_MSEL_GPCM \
 527                                 | CSPR_V)
 528
 529 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 530 #define CONFIG_SYS_CSOR3        0x0
 531
 532 /* CPLD Timing parameters for IFC CS3 */
 533 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 534                                         FTIM0_GPCM_TEADC(0x0e) | \
 535                                         FTIM0_GPCM_TEAHC(0x0e))
 536 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 537                                         FTIM1_GPCM_TRAD(0x1f))
 538 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 539                                         FTIM2_GPCM_TCH(0x8) | \
 540                                         FTIM2_GPCM_TWP(0x1f))
 541 #define CONFIG_SYS_CS3_FTIM3            0x0
 542
 543 #if defined(CONFIG_RAMBOOT_PBL)
 544 #define CONFIG_SYS_RAMBOOT
 545 #endif
 546
 547 /* I2C */
 548 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 549 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 550 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 551 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 552
 553 #define I2C_MUX_CH_DEFAULT      0x8
 554 #define I2C_MUX_CH_VOL_MONITOR  0xa
 555 #define I2C_MUX_CH_VSC3316_FS   0xc
 556 #define I2C_MUX_CH_VSC3316_BS   0xd
 557
 558 /* Voltage monitor on channel 2*/
 559 #define I2C_VOL_MONITOR_ADDR            0x40
 560 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 561 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 562 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 563
 564 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 565 #ifndef CONFIG_SPL_BUILD
 566 #define CONFIG_VID
 567 #endif
 568 #define CONFIG_VOL_MONITOR_IR36021_SET
 569 #define CONFIG_VOL_MONITOR_IR36021_READ
 570 /* The lowest and highest voltage allowed for T4240RDB */
 571 #define VDD_MV_MIN                      819
 572 #define VDD_MV_MAX                      1212
 573
 574 /*
 575  * eSPI - Enhanced SPI
 576  */
 577 #define CONFIG_SF_DEFAULT_SPEED         10000000
 578 #define CONFIG_SF_DEFAULT_MODE          0
 579
 580 /* Qman/Bman */
 581 #ifndef CONFIG_NOBQFMAN
 582 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 583 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 584 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 585 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 586 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 587 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 588 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 589 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 590 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 591 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 592                                         CONFIG_SYS_BMAN_CENA_SIZE)
 593 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 594 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 595 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 596 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 597 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 598 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 599 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 600 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 601 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 602 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 603 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 604                                         CONFIG_SYS_QMAN_CENA_SIZE)
 605 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 606 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 607
 608 #define CONFIG_SYS_DPAA_FMAN
 609 #define CONFIG_SYS_DPAA_PME
 610 #define CONFIG_SYS_PMAN
 611 #define CONFIG_SYS_DPAA_DCE
 612 #define CONFIG_SYS_DPAA_RMAN
 613 #define CONFIG_SYS_INTERLAKEN
 614
 615 /* Default address of microcode for the Linux Fman driver */
 616 #if defined(CONFIG_SPIFLASH)
 617 /*
 618  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 619  * env, so we got 0x110000.
 620  */
 621 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 622 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 623 #elif defined(CONFIG_SDCARD)
 624 /*
 625  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 626  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 627  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 628  */
 629 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 630 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 631 #elif defined(CONFIG_NAND)
 632 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 633 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 634 #else
 635 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 636 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 637 #endif
 638 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 639 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 640 #endif /* CONFIG_NOBQFMAN */
 641
 642 #ifdef CONFIG_SYS_DPAA_FMAN
 643 #define CONFIG_FMAN_ENET
 644 #define CONFIG_PHYLIB_10G
 645 #define CONFIG_PHY_VITESSE
 646 #define CONFIG_PHY_CORTINA
 647 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 648 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 649 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 650 #define CONFIG_PHY_TERANETICS
 651 #define SGMII_PHY_ADDR1 0x0
 652 #define SGMII_PHY_ADDR2 0x1
 653 #define SGMII_PHY_ADDR3 0x2
 654 #define SGMII_PHY_ADDR4 0x3
 655 #define SGMII_PHY_ADDR5 0x4
 656 #define SGMII_PHY_ADDR6 0x5
 657 #define SGMII_PHY_ADDR7 0x6
 658 #define SGMII_PHY_ADDR8 0x7
 659 #define FM1_10GEC1_PHY_ADDR     0x10
 660 #define FM1_10GEC2_PHY_ADDR     0x11
 661 #define FM2_10GEC1_PHY_ADDR     0x12
 662 #define FM2_10GEC2_PHY_ADDR     0x13
 663 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 664 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 665 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 666 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 667 #endif
 668
 669 /* SATA */
 670 #ifdef CONFIG_FSL_SATA_V2
 671 #define CONFIG_LIBATA
 672 #define CONFIG_FSL_SATA
 673
 674 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 675 #define CONFIG_SATA1
 676 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 677 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 678 #define CONFIG_SATA2
 679 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 680 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 681
 682 #define CONFIG_LBA48
 683 #define CONFIG_CMD_SATA
 684 #define CONFIG_DOS_PARTITION
 685 #endif
 686
 687 #ifdef CONFIG_FMAN_ENET
 688 #define CONFIG_MII              /* MII PHY management */
 689 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 690 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 691 #endif
 692
 693 /*
 694 * USB
 695 */
 696 #define CONFIG_USB_EHCI
 697 #define CONFIG_USB_EHCI_FSL
 698 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 699 #define CONFIG_HAS_FSL_DR_USB
 700
 701 #ifdef CONFIG_MMC
 702 #define CONFIG_FSL_ESDHC
 703 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 704 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 705 #define CONFIG_GENERIC_MMC
 706 #define CONFIG_DOS_PARTITION
 707 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 708 #endif
 709
 710 /* Hash command with SHA acceleration supported in hardware */
 711 #ifdef CONFIG_FSL_CAAM
 712 #define CONFIG_CMD_HASH
 713 #define CONFIG_SHA_HW_ACCEL
 714 #endif
 715
 716
 717 #define __USB_PHY_TYPE  utmi
 718
 719 /*
 720  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 721  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 722  * interleaving. It can be cacheline, page, bank, superbank.
 723  * See doc/README.fsl-ddr for details.
 724  */
 725 #ifdef CONFIG_ARCH_T4240
 726 #define CTRL_INTLV_PREFERED 3way_4KB
 727 #else
 728 #define CTRL_INTLV_PREFERED cacheline
 729 #endif
 730
 731 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 732         "hwconfig=fsl_ddr:"                                     \
 733         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 734         "bank_intlv=auto;"                                      \
 735         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 736         "netdev=eth0\0"                                         \
 737         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 738         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 739         "tftpflash=tftpboot $loadaddr $uboot && "               \
 740         "protect off $ubootaddr +$filesize && "                 \
 741         "erase $ubootaddr +$filesize && "                       \
 742         "cp.b $loadaddr $ubootaddr $filesize && "               \
 743         "protect on $ubootaddr +$filesize && "                  \
 744         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 745         "consoledev=ttyS0\0"                                    \
 746         "ramdiskaddr=2000000\0"                                 \
 747         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 748         "fdtaddr=1e00000\0"                                     \
 749         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 750         "bdev=sda3\0"
 751
 752 #define CONFIG_HVBOOT                                   \
 753         "setenv bootargs config-addr=0x60000000; "      \
 754         "bootm 0x01000000 - 0x00f00000"
 755
 756 #define CONFIG_LINUX                                    \
 757         "setenv bootargs root=/dev/ram rw "             \
 758         "console=$consoledev,$baudrate $othbootargs;"   \
 759         "setenv ramdiskaddr 0x02000000;"                \
 760         "setenv fdtaddr 0x00c00000;"                    \
 761         "setenv loadaddr 0x1000000;"                    \
 762         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 763
 764 #define CONFIG_HDBOOT                                   \
 765         "setenv bootargs root=/dev/$bdev rw "           \
 766         "console=$consoledev,$baudrate $othbootargs;"   \
 767         "tftp $loadaddr $bootfile;"                     \
 768         "tftp $fdtaddr $fdtfile;"                       \
 769         "bootm $loadaddr - $fdtaddr"
 770
 771 #define CONFIG_NFSBOOTCOMMAND                   \
 772         "setenv bootargs root=/dev/nfs rw "     \
 773         "nfsroot=$serverip:$rootpath "          \
 774         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 775         "console=$consoledev,$baudrate $othbootargs;"   \
 776         "tftp $loadaddr $bootfile;"             \
 777         "tftp $fdtaddr $fdtfile;"               \
 778         "bootm $loadaddr - $fdtaddr"
 779
 780 #define CONFIG_RAMBOOTCOMMAND                           \
 781         "setenv bootargs root=/dev/ram rw "             \
 782         "console=$consoledev,$baudrate $othbootargs;"   \
 783         "tftp $ramdiskaddr $ramdiskfile;"               \
 784         "tftp $loadaddr $bootfile;"                     \
 785         "tftp $fdtaddr $fdtfile;"                       \
 786         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 787
 788 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 789
 790 #include <asm/fsl_secure_boot.h>
 791
 792 #endif  /* __CONFIG_H */