include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifndef CONFIG_SDCARD
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #else
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24
  25 #ifdef  CONFIG_SDCARD
  26 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  27 #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  28 #define CFG_SYS_MMC_U_BOOT_DST  0x00200000
  29 #define CFG_SYS_MMC_U_BOOT_START        0x00200000
  30 #define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  31 #endif
  32
  33 #endif
  34 #endif /* CONFIG_RAMBOOT_PBL */
  35
  36 /* High Level Configuration Options */
  37
  38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  40 #endif
  41
  42 #define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
  43
  44 /*
  45  * These can be toggled for performance analysis, otherwise use default.
  46  */
  47 #ifdef CONFIG_DDR_ECC
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #endif
  50
  51 /*
  52  *  Config the L3 Cache as L3 SRAM
  53  */
  54 #define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  55 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  56
  57 #define CFG_SYS_DCSRBAR         0xf0000000
  58 #define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
  59
  60 /*
  61  * DDR Setup
  62  */
  63 #define CONFIG_VERY_BIG_RAM
  64 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  65 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  66
  67 /*
  68  * IFC Definitions
  69  */
  70 #define CFG_SYS_FLASH_BASE      0xe0000000
  71 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  72
  73 /* define to use L1 as initial stack */
  74 #define CONFIG_L1_INIT_RAM
  75 #define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
  76 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  77 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
  78 /* The assembler doesn't like typecast */
  79 #define CFG_SYS_INIT_RAM_ADDR_PHYS \
  80         ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  81           CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  82 #define CFG_SYS_INIT_RAM_SIZE           0x00004000
  83
  84 #define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85
  86 /* Serial Port - controlled on board with jumper J8
  87  * open - index 2
  88  * shorted - index 1
  89  */
  90 #define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
  91
  92 #define CFG_SYS_BAUDRATE_TABLE  \
  93         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  94
  95 #define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x11C500)
  96 #define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x11C600)
  97 #define CFG_SYS_NS16550_COM3    (CFG_SYS_CCSRBAR+0x11D500)
  98 #define CFG_SYS_NS16550_COM4    (CFG_SYS_CCSRBAR+0x11D600)
  99
 100 /* I2C */
 101
 102 /*
 103  * General PCI
 104  * Memory space is mapped 1-1, but I/O space must start from 0.
 105  */
 106
 107 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 108 #define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
 109 #define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 110 #define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 111 #define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 112
 113 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 114 #define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 115 #define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 116 #define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 117 #define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 118
 119 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 120 #define CFG_SYS_PCIE3_MEM_VIRT  0xc0000000
 121 #define CFG_SYS_PCIE3_MEM_PHYS  0xc40000000ull
 122
 123 /* controller 4, Base address 203000 */
 124 #define CFG_SYS_PCIE4_MEM_BUS   0xe0000000
 125 #define CFG_SYS_PCIE4_MEM_PHYS  0xc60000000ull
 126
 127 /*
 128  * Miscellaneous configurable options
 129  */
 130
 131 /*
 132  * For booting Linux, the board info and command line data
 133  * have to be in the first 64 MB of memory, since this is
 134  * the maximum mapped by the Linux kernel during initialization.
 135  */
 136 #define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 137
 138 /*
 139  * Environment Configuration
 140  */
 141 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 142 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 143
 144 #define HVBOOT                                  \
 145         "setenv bootargs config-addr=0x60000000; "      \
 146         "bootm 0x01000000 - 0x00f00000"
 147
 148 /*
 149  * DDR Setup
 150  */
 151 #define SPD_EEPROM_ADDRESS1     0x52
 152 #define SPD_EEPROM_ADDRESS2     0x54
 153 #define SPD_EEPROM_ADDRESS3     0x56
 154 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 155 #define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
 156
 157 /*
 158  * IFC Definitions
 159  */
 160 #define CFG_SYS_NOR0_CSPR_EXT   (0xf)
 161 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 162                                 + 0x8000000) | \
 163                                 CSPR_PORT_SIZE_16 | \
 164                                 CSPR_MSEL_NOR | \
 165                                 CSPR_V)
 166 #define CFG_SYS_NOR1_CSPR_EXT   (0xf)
 167 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 168                                 CSPR_PORT_SIZE_16 | \
 169                                 CSPR_MSEL_NOR | \
 170                                 CSPR_V)
 171 #define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 172 /* NOR Flash Timing Params */
 173 #define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 174
 175 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 176                                 FTIM0_NOR_TEADC(0x5) | \
 177                                 FTIM0_NOR_TEAHC(0x5))
 178 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 179                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 180                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 181 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 182                                 FTIM2_NOR_TCH(0x4) | \
 183                                 FTIM2_NOR_TWPH(0x0E) | \
 184                                 FTIM2_NOR_TWP(0x1c))
 185 #define CFG_SYS_NOR_FTIM3       0x0
 186
 187 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 188
 189 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS \
 190                                         + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
 191
 192 /* NAND Flash on IFC */
 193 #define CFG_SYS_NAND_BASE               0xff800000
 194 #define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 195
 196 #define CFG_SYS_NAND_CSPR_EXT   (0xf)
 197 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 198                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 199                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 200                                 | CSPR_V)
 201 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 202
 203 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 204                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 205                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 206                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 207                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 208                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 209                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 210
 211 /* ONFI NAND Flash mode0 Timing Params */
 212 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 213                                         FTIM0_NAND_TWP(0x18)   | \
 214                                         FTIM0_NAND_TWCHT(0x07) | \
 215                                         FTIM0_NAND_TWH(0x0a))
 216 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 217                                         FTIM1_NAND_TWBE(0x39)  | \
 218                                         FTIM1_NAND_TRR(0x0e)   | \
 219                                         FTIM1_NAND_TRP(0x18))
 220 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
 221                                         FTIM2_NAND_TREH(0x0a) | \
 222                                         FTIM2_NAND_TWHRE(0x1e))
 223 #define CFG_SYS_NAND_FTIM3              0x0
 224
 225 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 226
 227 #if defined(CONFIG_MTD_RAW_NAND)
 228 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 229 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 230 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 231 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 232 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 233 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 234 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 235 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 236 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR0_CSPR_EXT
 237 #define CFG_SYS_CSPR2           CFG_SYS_NOR0_CSPR
 238 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 239 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 240 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 241 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 242 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 243 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 244 #else
 245 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 246 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 247 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 248 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 249 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 250 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 251 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 252 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 253 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 254 #define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 255 #define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 256 #define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 257 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 258 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 259 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 260 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 261 #endif
 262 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 263 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 264 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 265 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 266 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 267 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 268 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 269 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 270
 271 /* CPLD on IFC */
 272 #define CFG_SYS_CPLD_BASE       0xffdf0000
 273 #define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 274 #define CFG_SYS_CSPR3_EXT       (0xf)
 275 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 276                                 | CSPR_PORT_SIZE_8 \
 277                                 | CSPR_MSEL_GPCM \
 278                                 | CSPR_V)
 279
 280 #define CFG_SYS_AMASK3  IFC_AMASK(64 * 1024)
 281 #define CFG_SYS_CSOR3   0x0
 282
 283 /* CPLD Timing parameters for IFC CS3 */
 284 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 285                                         FTIM0_GPCM_TEADC(0x0e) | \
 286                                         FTIM0_GPCM_TEAHC(0x0e))
 287 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 288                                         FTIM1_GPCM_TRAD(0x1f))
 289 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 290                                         FTIM2_GPCM_TCH(0x8) | \
 291                                         FTIM2_GPCM_TWP(0x1f))
 292 #define CFG_SYS_CS3_FTIM3               0x0
 293
 294 /* I2C */
 295 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 296 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 297
 298 #define I2C_MUX_CH_DEFAULT      0x8
 299 #define I2C_MUX_CH_VOL_MONITOR  0xa
 300 #define I2C_MUX_CH_VSC3316_FS   0xc
 301 #define I2C_MUX_CH_VSC3316_BS   0xd
 302
 303 /* Voltage monitor on channel 2*/
 304 #define I2C_VOL_MONITOR_ADDR            0x40
 305 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 306 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 307 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 308
 309 /* The lowest and highest voltage allowed for T4240RDB */
 310 #define VDD_MV_MIN                      819
 311 #define VDD_MV_MAX                      1212
 312
 313 /*
 314  * eSPI - Enhanced SPI
 315  */
 316
 317 /* Qman/Bman */
 318 #ifndef CONFIG_NOBQFMAN
 319 #define CFG_SYS_BMAN_NUM_PORTALS        50
 320 #define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 321 #define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 322 #define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 323 #define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 324 #define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 325 #define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 326 #define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 327 #define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 328                                         CFG_SYS_BMAN_CENA_SIZE)
 329 #define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 330 #define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
 331 #define CFG_SYS_QMAN_NUM_PORTALS        50
 332 #define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 333 #define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 334 #define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 335 #define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 336 #define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 337 #define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 338                                         CFG_SYS_QMAN_CENA_SIZE)
 339 #define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 340 #define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 341 #endif /* CONFIG_NOBQFMAN */
 342
 343 #ifdef CONFIG_SYS_DPAA_FMAN
 344 #define SGMII_PHY_ADDR1 0x0
 345 #define SGMII_PHY_ADDR2 0x1
 346 #define SGMII_PHY_ADDR3 0x2
 347 #define SGMII_PHY_ADDR4 0x3
 348 #define SGMII_PHY_ADDR5 0x4
 349 #define SGMII_PHY_ADDR6 0x5
 350 #define SGMII_PHY_ADDR7 0x6
 351 #define SGMII_PHY_ADDR8 0x7
 352 #define FM1_10GEC1_PHY_ADDR     0x10
 353 #define FM1_10GEC2_PHY_ADDR     0x11
 354 #define FM2_10GEC1_PHY_ADDR     0x12
 355 #define FM2_10GEC2_PHY_ADDR     0x13
 356 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 357 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 358 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 359 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 360 #endif
 361
 362 /*
 363 * USB
 364 */
 365
 366 #ifdef CONFIG_MMC
 367 #define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 368 #endif
 369
 370
 371 #define __USB_PHY_TYPE  utmi
 372
 373 /*
 374  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 375  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 376  * interleaving. It can be cacheline, page, bank, superbank.
 377  * See doc/README.fsl-ddr for details.
 378  */
 379 #ifdef CONFIG_ARCH_T4240
 380 #define CTRL_INTLV_PREFERED 3way_4KB
 381 #else
 382 #define CTRL_INTLV_PREFERED cacheline
 383 #endif
 384
 385 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 386         "hwconfig=fsl_ddr:"                                     \
 387         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 388         "bank_intlv=auto;"                                      \
 389         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 390         "netdev=eth0\0"                                         \
 391         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 392         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 393         "tftpflash=tftpboot $loadaddr $uboot && "               \
 394         "protect off $ubootaddr +$filesize && "                 \
 395         "erase $ubootaddr +$filesize && "                       \
 396         "cp.b $loadaddr $ubootaddr $filesize && "               \
 397         "protect on $ubootaddr +$filesize && "                  \
 398         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 399         "consoledev=ttyS0\0"                                    \
 400         "ramdiskaddr=2000000\0"                                 \
 401         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 402         "fdtaddr=1e00000\0"                                     \
 403         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 404         "bdev=sda3\0"
 405
 406 #define HVBOOT                                  \
 407         "setenv bootargs config-addr=0x60000000; "      \
 408         "bootm 0x01000000 - 0x00f00000"
 409
 410 #include <asm/fsl_secure_boot.h>
 411
 412 #endif  /* __CONFIG_H */