include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE4
  17
  18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  22 #ifndef CONFIG_SDCARD
  23 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  24 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  25 #else
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_PAD_TO               0x40000
  28 #define CONFIG_SPL_MAX_SIZE             0x28000
  29 #define RESET_VECTOR_OFFSET             0x27FFC
  30 #define BOOT_PAGE_OFFSET                0x27000
  31
  32 #ifdef  CONFIG_SDCARD
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  34 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  35 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  36 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  37 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  38 #ifndef CONFIG_SPL_BUILD
  39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  40 #endif
  41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  42 #endif
  43
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #endif
  51 #endif /* CONFIG_RAMBOOT_PBL */
  52
  53 #define CONFIG_DDR_ECC
  54
  55 /* High Level Configuration Options */
  56 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  65 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  66 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  67 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_SYS_CACHE_STASHING
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  76 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  77 #endif
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS
  80
  81 /*
  82  *  Config the L3 Cache as L3 SRAM
  83  */
  84 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  85 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  86 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  87 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  88 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  89 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  90 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  91
  92 #define CONFIG_SYS_DCSRBAR              0xf0000000
  93 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  94
  95 /*
  96  * DDR Setup
  97  */
  98 #define CONFIG_VERY_BIG_RAM
  99 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 100 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 101
 102 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 103 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 104
 105 #define CONFIG_DDR_SPD
 106
 107 /*
 108  * IFC Definitions
 109  */
 110 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 111 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 112
 113 #ifdef CONFIG_SPL_BUILD
 114 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 115 #else
 116 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 117 #endif
 118
 119 #define CONFIG_HWCONFIG
 120
 121 /* define to use L1 as initial stack */
 122 #define CONFIG_L1_INIT_RAM
 123 #define CONFIG_SYS_INIT_RAM_LOCK
 124 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 127 /* The assembler doesn't like typecast */
 128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 129         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 130           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 131 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 132
 133 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 134                                         GENERATED_GBL_DATA_SIZE)
 135 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 136
 137 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 138 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 139
 140 /* Serial Port - controlled on board with jumper J8
 141  * open - index 2
 142  * shorted - index 1
 143  */
 144 #define CONFIG_SYS_NS16550_SERIAL
 145 #define CONFIG_SYS_NS16550_REG_SIZE     1
 146 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 147
 148 #define CONFIG_SYS_BAUDRATE_TABLE       \
 149         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 150
 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 155
 156 /* I2C */
 157 #if !CONFIG_IS_ENABLED(DM_I2C)
 158 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 159 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 160 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 161 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 162 #else
 163 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 164 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 165 #endif
 166
 167 #define CONFIG_SYS_I2C_FSL
 168
 169 /*
 170  * General PCI
 171  * Memory space is mapped 1-1, but I/O space must start from 0.
 172  */
 173
 174 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 175 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 176 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 177 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 178 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 179
 180 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 181 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 182 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 183 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 184 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 185
 186 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 187 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 188 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 189 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 190 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 191
 192 /* controller 4, Base address 203000 */
 193 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 194 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 195 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 196
 197 #ifdef CONFIG_PCI
 198 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 199 #endif  /* CONFIG_PCI */
 200
 201 /* SATA */
 202 #ifdef CONFIG_FSL_SATA_V2
 203 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 204 #define CONFIG_SATA1
 205 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 206 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 207 #define CONFIG_SATA2
 208 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 209 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 210
 211 #define CONFIG_LBA48
 212 #endif
 213
 214 #ifdef CONFIG_FMAN_ENET
 215 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 216 #endif
 217
 218 /*
 219  * Environment
 220  */
 221 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 222 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 223
 224 /*
 225  * Miscellaneous configurable options
 226  */
 227 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 228
 229 /*
 230  * For booting Linux, the board info and command line data
 231  * have to be in the first 64 MB of memory, since this is
 232  * the maximum mapped by the Linux kernel during initialization.
 233  */
 234 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 235 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 236
 237 #ifdef CONFIG_CMD_KGDB
 238 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 239 #endif
 240
 241 /*
 242  * Environment Configuration
 243  */
 244 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 245 #define CONFIG_BOOTFILE         "uImage"
 246 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 247
 248 /* default location for tftp and bootm */
 249 #define CONFIG_LOADADDR         1000000
 250
 251 #define CONFIG_HVBOOT                                   \
 252         "setenv bootargs config-addr=0x60000000; "      \
 253         "bootm 0x01000000 - 0x00f00000"
 254
 255 #define CONFIG_SYS_CLK_FREQ     66666666
 256 #define CONFIG_DDR_CLK_FREQ     133333333
 257
 258 #ifndef __ASSEMBLY__
 259 unsigned long get_board_sys_clk(void);
 260 unsigned long get_board_ddr_clk(void);
 261 #endif
 262
 263 /*
 264  * DDR Setup
 265  */
 266 #define CONFIG_SYS_SPD_BUS_NUM  0
 267 #define SPD_EEPROM_ADDRESS1     0x52
 268 #define SPD_EEPROM_ADDRESS2     0x54
 269 #define SPD_EEPROM_ADDRESS3     0x56
 270 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 271 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 272
 273 /*
 274  * IFC Definitions
 275  */
 276 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 277 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 278                                 + 0x8000000) | \
 279                                 CSPR_PORT_SIZE_16 | \
 280                                 CSPR_MSEL_NOR | \
 281                                 CSPR_V)
 282 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 283 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 284                                 CSPR_PORT_SIZE_16 | \
 285                                 CSPR_MSEL_NOR | \
 286                                 CSPR_V)
 287 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 288 /* NOR Flash Timing Params */
 289 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 290
 291 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 292                                 FTIM0_NOR_TEADC(0x5) | \
 293                                 FTIM0_NOR_TEAHC(0x5))
 294 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 295                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 296                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 297 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 298                                 FTIM2_NOR_TCH(0x4) | \
 299                                 FTIM2_NOR_TWPH(0x0E) | \
 300                                 FTIM2_NOR_TWP(0x1c))
 301 #define CONFIG_SYS_NOR_FTIM3    0x0
 302
 303 #define CONFIG_SYS_FLASH_QUIET_TEST
 304 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 305
 306 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 307 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 308 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 309 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 310
 311 #define CONFIG_SYS_FLASH_EMPTY_INFO
 312 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 313                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 314
 315 /* NAND Flash on IFC */
 316 #define CONFIG_NAND_FSL_IFC
 317 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 318 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 319 #define CONFIG_SYS_NAND_BASE            0xff800000
 320 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 321
 322 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 323 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 324                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 325                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 326                                 | CSPR_V)
 327 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 328
 329 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 330                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 331                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 332                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 333                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 334                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 335                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 336
 337 #define CONFIG_SYS_NAND_ONFI_DETECTION
 338
 339 /* ONFI NAND Flash mode0 Timing Params */
 340 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 341                                         FTIM0_NAND_TWP(0x18)   | \
 342                                         FTIM0_NAND_TWCHT(0x07) | \
 343                                         FTIM0_NAND_TWH(0x0a))
 344 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 345                                         FTIM1_NAND_TWBE(0x39)  | \
 346                                         FTIM1_NAND_TRR(0x0e)   | \
 347                                         FTIM1_NAND_TRP(0x18))
 348 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 349                                         FTIM2_NAND_TREH(0x0a) | \
 350                                         FTIM2_NAND_TWHRE(0x1e))
 351 #define CONFIG_SYS_NAND_FTIM3           0x0
 352
 353 #define CONFIG_SYS_NAND_DDR_LAW         11
 354 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 355 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 356
 357 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 358
 359 #if defined(CONFIG_MTD_RAW_NAND)
 360 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 361 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 362 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 363 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 364 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 365 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 366 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 367 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 368 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 369 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 370 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 371 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 372 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 373 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 374 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 375 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 376 #else
 377 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 378 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 379 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 380 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 381 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 382 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 383 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 384 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 385 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 386 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 387 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 388 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 389 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 390 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 391 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 392 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 393 #endif
 394 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 395 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 396 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 397 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 398 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 399 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 400 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 401 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 402
 403 /* CPLD on IFC */
 404 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 405 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 406 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 407 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 408                                 | CSPR_PORT_SIZE_8 \
 409                                 | CSPR_MSEL_GPCM \
 410                                 | CSPR_V)
 411
 412 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 413 #define CONFIG_SYS_CSOR3        0x0
 414
 415 /* CPLD Timing parameters for IFC CS3 */
 416 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 417                                         FTIM0_GPCM_TEADC(0x0e) | \
 418                                         FTIM0_GPCM_TEAHC(0x0e))
 419 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 420                                         FTIM1_GPCM_TRAD(0x1f))
 421 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 422                                         FTIM2_GPCM_TCH(0x8) | \
 423                                         FTIM2_GPCM_TWP(0x1f))
 424 #define CONFIG_SYS_CS3_FTIM3            0x0
 425
 426 #if defined(CONFIG_RAMBOOT_PBL)
 427 #define CONFIG_SYS_RAMBOOT
 428 #endif
 429
 430 /* I2C */
 431 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 432 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 433 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 434 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 435
 436 #define I2C_MUX_CH_DEFAULT      0x8
 437 #define I2C_MUX_CH_VOL_MONITOR  0xa
 438 #define I2C_MUX_CH_VSC3316_FS   0xc
 439 #define I2C_MUX_CH_VSC3316_BS   0xd
 440
 441 /* Voltage monitor on channel 2*/
 442 #define I2C_VOL_MONITOR_ADDR            0x40
 443 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 444 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 445 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 446
 447 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 448 #ifndef CONFIG_SPL_BUILD
 449 #define CONFIG_VID
 450 #endif
 451 #define CONFIG_VOL_MONITOR_IR36021_SET
 452 #define CONFIG_VOL_MONITOR_IR36021_READ
 453 /* The lowest and highest voltage allowed for T4240RDB */
 454 #define VDD_MV_MIN                      819
 455 #define VDD_MV_MAX                      1212
 456
 457 /*
 458  * eSPI - Enhanced SPI
 459  */
 460
 461 /* Qman/Bman */
 462 #ifndef CONFIG_NOBQFMAN
 463 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 464 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 465 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 466 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 467 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 468 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 469 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 470 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 471 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 472                                         CONFIG_SYS_BMAN_CENA_SIZE)
 473 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 474 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 475 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 476 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 477 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 478 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 479 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 480 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 481 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 482 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 483 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 484                                         CONFIG_SYS_QMAN_CENA_SIZE)
 485 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 486 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 487
 488 #define CONFIG_SYS_DPAA_FMAN
 489 #define CONFIG_SYS_DPAA_PME
 490 #define CONFIG_SYS_PMAN
 491 #define CONFIG_SYS_DPAA_DCE
 492 #define CONFIG_SYS_DPAA_RMAN
 493 #define CONFIG_SYS_INTERLAKEN
 494
 495 /* Default address of microcode for the Linux Fman driver */
 496 #if defined(CONFIG_SPIFLASH)
 497 /*
 498  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 499  * env, so we got 0x110000.
 500  */
 501 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 502 #elif defined(CONFIG_SDCARD)
 503 /*
 504  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 505  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 506  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 507  */
 508 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 509 #elif defined(CONFIG_MTD_RAW_NAND)
 510 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 511 #else
 512 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 513 #endif
 514 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 515 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 516 #endif /* CONFIG_NOBQFMAN */
 517
 518 #ifdef CONFIG_SYS_DPAA_FMAN
 519 #define SGMII_PHY_ADDR1 0x0
 520 #define SGMII_PHY_ADDR2 0x1
 521 #define SGMII_PHY_ADDR3 0x2
 522 #define SGMII_PHY_ADDR4 0x3
 523 #define SGMII_PHY_ADDR5 0x4
 524 #define SGMII_PHY_ADDR6 0x5
 525 #define SGMII_PHY_ADDR7 0x6
 526 #define SGMII_PHY_ADDR8 0x7
 527 #define FM1_10GEC1_PHY_ADDR     0x10
 528 #define FM1_10GEC2_PHY_ADDR     0x11
 529 #define FM2_10GEC1_PHY_ADDR     0x12
 530 #define FM2_10GEC2_PHY_ADDR     0x13
 531 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 532 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 533 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 534 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 535 #endif
 536
 537 /* SATA */
 538 #ifdef CONFIG_FSL_SATA_V2
 539 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 540 #define CONFIG_SATA1
 541 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 542 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 543 #define CONFIG_SATA2
 544 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 545 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 546
 547 #define CONFIG_LBA48
 548 #endif
 549
 550 #ifdef CONFIG_FMAN_ENET
 551 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 552 #endif
 553
 554 /*
 555 * USB
 556 */
 557 #define CONFIG_USB_EHCI_FSL
 558 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 559 #define CONFIG_HAS_FSL_DR_USB
 560
 561 #ifdef CONFIG_MMC
 562 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 563 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 564 #endif
 565
 566
 567 #define __USB_PHY_TYPE  utmi
 568
 569 /*
 570  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 571  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 572  * interleaving. It can be cacheline, page, bank, superbank.
 573  * See doc/README.fsl-ddr for details.
 574  */
 575 #ifdef CONFIG_ARCH_T4240
 576 #define CTRL_INTLV_PREFERED 3way_4KB
 577 #else
 578 #define CTRL_INTLV_PREFERED cacheline
 579 #endif
 580
 581 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 582         "hwconfig=fsl_ddr:"                                     \
 583         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 584         "bank_intlv=auto;"                                      \
 585         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 586         "netdev=eth0\0"                                         \
 587         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 588         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 589         "tftpflash=tftpboot $loadaddr $uboot && "               \
 590         "protect off $ubootaddr +$filesize && "                 \
 591         "erase $ubootaddr +$filesize && "                       \
 592         "cp.b $loadaddr $ubootaddr $filesize && "               \
 593         "protect on $ubootaddr +$filesize && "                  \
 594         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 595         "consoledev=ttyS0\0"                                    \
 596         "ramdiskaddr=2000000\0"                                 \
 597         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 598         "fdtaddr=1e00000\0"                                     \
 599         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 600         "bdev=sda3\0"
 601
 602 #define CONFIG_HVBOOT                                   \
 603         "setenv bootargs config-addr=0x60000000; "      \
 604         "bootm 0x01000000 - 0x00f00000"
 605
 606 #define CONFIG_LINUX                                    \
 607         "setenv bootargs root=/dev/ram rw "             \
 608         "console=$consoledev,$baudrate $othbootargs;"   \
 609         "setenv ramdiskaddr 0x02000000;"                \
 610         "setenv fdtaddr 0x00c00000;"                    \
 611         "setenv loadaddr 0x1000000;"                    \
 612         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 613
 614 #define CONFIG_HDBOOT                                   \
 615         "setenv bootargs root=/dev/$bdev rw "           \
 616         "console=$consoledev,$baudrate $othbootargs;"   \
 617         "tftp $loadaddr $bootfile;"                     \
 618         "tftp $fdtaddr $fdtfile;"                       \
 619         "bootm $loadaddr - $fdtaddr"
 620
 621 #define CONFIG_NFSBOOTCOMMAND                   \
 622         "setenv bootargs root=/dev/nfs rw "     \
 623         "nfsroot=$serverip:$rootpath "          \
 624         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 625         "console=$consoledev,$baudrate $othbootargs;"   \
 626         "tftp $loadaddr $bootfile;"             \
 627         "tftp $fdtaddr $fdtfile;"               \
 628         "bootm $loadaddr - $fdtaddr"
 629
 630 #define CONFIG_RAMBOOTCOMMAND                           \
 631         "setenv bootargs root=/dev/ram rw "             \
 632         "console=$consoledev,$baudrate $othbootargs;"   \
 633         "tftp $ramdiskaddr $ramdiskfile;"               \
 634         "tftp $loadaddr $bootfile;"                     \
 635         "tftp $fdtaddr $fdtfile;"                       \
 636         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 637
 638 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 639
 640 #include <asm/fsl_secure_boot.h>
 641
 642 #endif  /* __CONFIG_H */