1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
38 #ifndef CONFIG_SPL_BUILD
39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #endif /* CONFIG_RAMBOOT_PBL */
53 #define CONFIG_DDR_ECC
55 /* High Level Configuration Options */
56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1 /* PCIE controller 1 */
65 #define CONFIG_PCIE2 /* PCIE controller 2 */
66 #define CONFIG_PCIE3 /* PCIE controller 3 */
67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_SYS_CACHE_STASHING
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
76 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79 #define CONFIG_ENABLE_36BIT_PHYS
82 * Config the L3 Cache as L3 SRAM
84 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
85 #define CONFIG_SYS_L3_SIZE (512 << 10)
86 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
87 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
88 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
89 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
90 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
92 #define CONFIG_SYS_DCSRBAR 0xf0000000
93 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
98 #define CONFIG_VERY_BIG_RAM
99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
103 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
105 #define CONFIG_DDR_SPD
110 #define CONFIG_SYS_FLASH_BASE 0xe0000000
111 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
113 #ifdef CONFIG_SPL_BUILD
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
119 #define CONFIG_HWCONFIG
121 /* define to use L1 as initial stack */
122 #define CONFIG_L1_INIT_RAM
123 #define CONFIG_SYS_INIT_RAM_LOCK
124 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
127 /* The assembler doesn't like typecast */
128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
129 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
130 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
131 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
134 GENERATED_GBL_DATA_SIZE)
135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
137 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
138 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
140 /* Serial Port - controlled on board with jumper J8
144 #define CONFIG_SYS_NS16550_SERIAL
145 #define CONFIG_SYS_NS16550_REG_SIZE 1
146 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
148 #define CONFIG_SYS_BAUDRATE_TABLE \
149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
157 #if CONFIG_IS_ENABLED(DM_I2C)
158 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
159 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
164 * Memory space is mapped 1-1, but I/O space must start from 0.
167 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
168 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
169 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
170 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
171 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
173 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
174 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
175 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
176 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
177 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
179 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
180 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
181 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
182 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
183 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
185 /* controller 4, Base address 203000 */
186 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
187 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
188 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
191 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
192 #endif /* CONFIG_PCI */
195 #ifdef CONFIG_FSL_SATA_V2
196 #define CONFIG_SYS_SATA_MAX_DEVICE 2
198 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
199 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
201 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
202 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
207 #ifdef CONFIG_FMAN_ENET
208 #define CONFIG_ETHPRIME "FM1@DTSEC1"
214 #define CONFIG_LOADS_ECHO /* echo on for serial download */
215 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
218 * Miscellaneous configurable options
220 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
223 * For booting Linux, the board info and command line data
224 * have to be in the first 64 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
227 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
228 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
230 #ifdef CONFIG_CMD_KGDB
231 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
235 * Environment Configuration
237 #define CONFIG_ROOTPATH "/opt/nfsroot"
238 #define CONFIG_BOOTFILE "uImage"
239 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
241 /* default location for tftp and bootm */
242 #define CONFIG_LOADADDR 1000000
244 #define CONFIG_HVBOOT \
245 "setenv bootargs config-addr=0x60000000; " \
246 "bootm 0x01000000 - 0x00f00000"
248 #define CONFIG_SYS_CLK_FREQ 66666666
249 #define CONFIG_DDR_CLK_FREQ 133333333
252 unsigned long get_board_sys_clk(void);
253 unsigned long get_board_ddr_clk(void);
259 #define CONFIG_SYS_SPD_BUS_NUM 0
260 #define SPD_EEPROM_ADDRESS1 0x52
261 #define SPD_EEPROM_ADDRESS2 0x54
262 #define SPD_EEPROM_ADDRESS3 0x56
263 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
264 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
269 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
270 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
272 CSPR_PORT_SIZE_16 | \
275 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
276 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
277 CSPR_PORT_SIZE_16 | \
280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
281 /* NOR Flash Timing Params */
282 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
284 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
285 FTIM0_NOR_TEADC(0x5) | \
286 FTIM0_NOR_TEAHC(0x5))
287 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
288 FTIM1_NOR_TRAD_NOR(0x1A) |\
289 FTIM1_NOR_TSEQRAD_NOR(0x13))
290 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
291 FTIM2_NOR_TCH(0x4) | \
292 FTIM2_NOR_TWPH(0x0E) | \
294 #define CONFIG_SYS_NOR_FTIM3 0x0
296 #define CONFIG_SYS_FLASH_QUIET_TEST
297 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
299 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
300 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
301 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
302 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
304 #define CONFIG_SYS_FLASH_EMPTY_INFO
305 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
306 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
308 /* NAND Flash on IFC */
309 #define CONFIG_NAND_FSL_IFC
310 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
311 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
312 #define CONFIG_SYS_NAND_BASE 0xff800000
313 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
315 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
316 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
317 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
318 | CSPR_MSEL_NAND /* MSEL = NAND */ \
320 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
322 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
323 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
324 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
325 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
326 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
327 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
328 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
330 #define CONFIG_SYS_NAND_ONFI_DETECTION
332 /* ONFI NAND Flash mode0 Timing Params */
333 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
334 FTIM0_NAND_TWP(0x18) | \
335 FTIM0_NAND_TWCHT(0x07) | \
336 FTIM0_NAND_TWH(0x0a))
337 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
338 FTIM1_NAND_TWBE(0x39) | \
339 FTIM1_NAND_TRR(0x0e) | \
340 FTIM1_NAND_TRP(0x18))
341 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
342 FTIM2_NAND_TREH(0x0a) | \
343 FTIM2_NAND_TWHRE(0x1e))
344 #define CONFIG_SYS_NAND_FTIM3 0x0
346 #define CONFIG_SYS_NAND_DDR_LAW 11
347 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
348 #define CONFIG_SYS_MAX_NAND_DEVICE 1
350 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
352 #if defined(CONFIG_MTD_RAW_NAND)
353 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
361 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
362 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
363 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
364 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
365 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
366 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
367 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
368 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
370 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
371 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
372 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
373 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
374 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
375 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
376 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
377 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
378 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
379 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
380 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
381 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
382 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
383 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
384 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
385 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
387 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
388 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
389 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
390 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
391 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
392 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
393 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
394 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
397 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
398 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
399 #define CONFIG_SYS_CSPR3_EXT (0xf)
400 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
405 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
406 #define CONFIG_SYS_CSOR3 0x0
408 /* CPLD Timing parameters for IFC CS3 */
409 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
410 FTIM0_GPCM_TEADC(0x0e) | \
411 FTIM0_GPCM_TEAHC(0x0e))
412 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
413 FTIM1_GPCM_TRAD(0x1f))
414 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
415 FTIM2_GPCM_TCH(0x8) | \
416 FTIM2_GPCM_TWP(0x1f))
417 #define CONFIG_SYS_CS3_FTIM3 0x0
419 #if defined(CONFIG_RAMBOOT_PBL)
420 #define CONFIG_SYS_RAMBOOT
424 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
425 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
427 #define I2C_MUX_CH_DEFAULT 0x8
428 #define I2C_MUX_CH_VOL_MONITOR 0xa
429 #define I2C_MUX_CH_VSC3316_FS 0xc
430 #define I2C_MUX_CH_VSC3316_BS 0xd
432 /* Voltage monitor on channel 2*/
433 #define I2C_VOL_MONITOR_ADDR 0x40
434 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
435 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
436 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
438 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
439 #ifndef CONFIG_SPL_BUILD
442 #define CONFIG_VOL_MONITOR_IR36021_SET
443 #define CONFIG_VOL_MONITOR_IR36021_READ
444 /* The lowest and highest voltage allowed for T4240RDB */
445 #define VDD_MV_MIN 819
446 #define VDD_MV_MAX 1212
449 * eSPI - Enhanced SPI
453 #ifndef CONFIG_NOBQFMAN
454 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
455 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
456 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
457 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
458 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
459 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
460 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
461 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
462 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
463 CONFIG_SYS_BMAN_CENA_SIZE)
464 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
465 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
466 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
467 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
468 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
469 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
470 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
471 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
472 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
473 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
474 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
475 CONFIG_SYS_QMAN_CENA_SIZE)
476 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
477 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
479 #define CONFIG_SYS_DPAA_FMAN
480 #define CONFIG_SYS_DPAA_PME
481 #define CONFIG_SYS_PMAN
482 #define CONFIG_SYS_DPAA_DCE
483 #define CONFIG_SYS_DPAA_RMAN
484 #define CONFIG_SYS_INTERLAKEN
486 /* Default address of microcode for the Linux Fman driver */
487 #if defined(CONFIG_SPIFLASH)
489 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
490 * env, so we got 0x110000.
492 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
493 #elif defined(CONFIG_SDCARD)
495 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
496 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
497 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
499 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
500 #elif defined(CONFIG_MTD_RAW_NAND)
501 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
503 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
505 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
506 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
507 #endif /* CONFIG_NOBQFMAN */
509 #ifdef CONFIG_SYS_DPAA_FMAN
510 #define SGMII_PHY_ADDR1 0x0
511 #define SGMII_PHY_ADDR2 0x1
512 #define SGMII_PHY_ADDR3 0x2
513 #define SGMII_PHY_ADDR4 0x3
514 #define SGMII_PHY_ADDR5 0x4
515 #define SGMII_PHY_ADDR6 0x5
516 #define SGMII_PHY_ADDR7 0x6
517 #define SGMII_PHY_ADDR8 0x7
518 #define FM1_10GEC1_PHY_ADDR 0x10
519 #define FM1_10GEC2_PHY_ADDR 0x11
520 #define FM2_10GEC1_PHY_ADDR 0x12
521 #define FM2_10GEC2_PHY_ADDR 0x13
522 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
523 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
524 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
525 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
529 #ifdef CONFIG_FSL_SATA_V2
530 #define CONFIG_SYS_SATA_MAX_DEVICE 2
532 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
533 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
535 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
536 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
541 #ifdef CONFIG_FMAN_ENET
542 #define CONFIG_ETHPRIME "FM1@DTSEC1"
548 #define CONFIG_USB_EHCI_FSL
549 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
550 #define CONFIG_HAS_FSL_DR_USB
553 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
554 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
558 #define __USB_PHY_TYPE utmi
561 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
562 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
563 * interleaving. It can be cacheline, page, bank, superbank.
564 * See doc/README.fsl-ddr for details.
566 #ifdef CONFIG_ARCH_T4240
567 #define CTRL_INTLV_PREFERED 3way_4KB
569 #define CTRL_INTLV_PREFERED cacheline
572 #define CONFIG_EXTRA_ENV_SETTINGS \
573 "hwconfig=fsl_ddr:" \
574 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
576 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
578 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
579 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
580 "tftpflash=tftpboot $loadaddr $uboot && " \
581 "protect off $ubootaddr +$filesize && " \
582 "erase $ubootaddr +$filesize && " \
583 "cp.b $loadaddr $ubootaddr $filesize && " \
584 "protect on $ubootaddr +$filesize && " \
585 "cmp.b $loadaddr $ubootaddr $filesize\0" \
586 "consoledev=ttyS0\0" \
587 "ramdiskaddr=2000000\0" \
588 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
589 "fdtaddr=1e00000\0" \
590 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
593 #define CONFIG_HVBOOT \
594 "setenv bootargs config-addr=0x60000000; " \
595 "bootm 0x01000000 - 0x00f00000"
597 #define CONFIG_LINUX \
598 "setenv bootargs root=/dev/ram rw " \
599 "console=$consoledev,$baudrate $othbootargs;" \
600 "setenv ramdiskaddr 0x02000000;" \
601 "setenv fdtaddr 0x00c00000;" \
602 "setenv loadaddr 0x1000000;" \
603 "bootm $loadaddr $ramdiskaddr $fdtaddr"
605 #define CONFIG_HDBOOT \
606 "setenv bootargs root=/dev/$bdev rw " \
607 "console=$consoledev,$baudrate $othbootargs;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $fdtaddr $fdtfile;" \
610 "bootm $loadaddr - $fdtaddr"
612 #define CONFIG_NFSBOOTCOMMAND \
613 "setenv bootargs root=/dev/nfs rw " \
614 "nfsroot=$serverip:$rootpath " \
615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
616 "console=$consoledev,$baudrate $othbootargs;" \
617 "tftp $loadaddr $bootfile;" \
618 "tftp $fdtaddr $fdtfile;" \
619 "bootm $loadaddr - $fdtaddr"
621 #define CONFIG_RAMBOOTCOMMAND \
622 "setenv bootargs root=/dev/ram rw " \
623 "console=$consoledev,$baudrate $othbootargs;" \
624 "tftp $ramdiskaddr $ramdiskfile;" \
625 "tftp $loadaddr $bootfile;" \
626 "tftp $fdtaddr $fdtfile;" \
627 "bootm $loadaddr $ramdiskaddr $fdtaddr"
629 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
631 #include <asm/fsl_secure_boot.h>
633 #endif /* __CONFIG_H */