include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19
  20 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  21
  22 #ifdef CONFIG_RAMBOOT_PBL
  23 #define RESET_VECTOR_OFFSET             0x27FFC
  24 #define BOOT_PAGE_OFFSET                0x27000
  25
  26 #ifdef CONFIG_MTD_RAW_NAND
  27 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  28 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  29 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  30 #endif
  31
  32 #ifdef CONFIG_SPIFLASH
  33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  38 #endif
  39
  40 #ifdef CONFIG_SDCARD
  41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  44 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  46 #endif
  47
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  52 /* Set 1M boot space */
  53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  55                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  57 #endif
  58
  59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  61 #endif
  62
  63 /*
  64  * These can be toggled for performance analysis, otherwise use default.
  65  */
  66 #ifdef CONFIG_DDR_ECC
  67 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  68 #endif
  69
  70 /*
  71  * Config the L3 Cache as L3 SRAM
  72  */
  73 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  74 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  75 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  76
  77 #define CONFIG_SYS_DCSRBAR      0xf0000000
  78 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  79
  80 /*
  81  * DDR Setup
  82  */
  83 #define CONFIG_VERY_BIG_RAM
  84 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  85 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  86 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  87 #define SPD_EEPROM_ADDRESS1     0x51
  88 #define SPD_EEPROM_ADDRESS2     0x52
  89 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  90 #define CTRL_INTLV_PREFERED     cacheline
  91
  92 /*
  93  * IFC Definitions
  94  */
  95 #define CONFIG_SYS_FLASH_BASE           0xe8000000
  96 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  97 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
  98 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  99                                 CSPR_PORT_SIZE_16 | \
 100                                 CSPR_MSEL_NOR | \
 101                                 CSPR_V)
 102 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 103
 104 /* NOR Flash Timing Params */
 105 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 106
 107 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 108                                 FTIM0_NOR_TEADC(0x5) | \
 109                                 FTIM0_NOR_TEAHC(0x5))
 110 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 111                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 112                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 113 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 114                                 FTIM2_NOR_TCH(0x4) | \
 115                                 FTIM2_NOR_TWPH(0x0E) | \
 116                                 FTIM2_NOR_TWP(0x1c))
 117 #define CONFIG_SYS_NOR_FTIM3    0x0
 118
 119 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 120
 121 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 122
 123 /* CPLD on IFC */
 124 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 125 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 126 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 127 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 128                                 | CSPR_PORT_SIZE_8 \
 129                                 | CSPR_MSEL_GPCM \
 130                                 | CSPR_V)
 131 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 132 #define CONFIG_SYS_CSOR2        0x0
 133
 134 /* CPLD Timing parameters for IFC CS2 */
 135 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 136                                         FTIM0_GPCM_TEADC(0x0e) | \
 137                                         FTIM0_GPCM_TEAHC(0x0e))
 138 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 139                                         FTIM1_GPCM_TRAD(0x1f))
 140 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 141                                         FTIM2_GPCM_TCH(0x8) | \
 142                                         FTIM2_GPCM_TWP(0x1f))
 143 #define CONFIG_SYS_CS2_FTIM3            0x0
 144
 145 /* NAND Flash on IFC */
 146 #define CONFIG_SYS_NAND_BASE            0xff800000
 147 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 148
 149 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 150 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 151                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 152                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 153                                 | CSPR_V)
 154 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 155
 156 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 157                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 158                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 159                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 160                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 161                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 162                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 163
 164 /* ONFI NAND Flash mode0 Timing Params */
 165 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 166                                         FTIM0_NAND_TWP(0x18)    | \
 167                                         FTIM0_NAND_TWCHT(0x07)  | \
 168                                         FTIM0_NAND_TWH(0x0a))
 169 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 170                                         FTIM1_NAND_TWBE(0x39)   | \
 171                                         FTIM1_NAND_TRR(0x0e)    | \
 172                                         FTIM1_NAND_TRP(0x18))
 173 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 174                                         FTIM2_NAND_TREH(0x0a)   | \
 175                                         FTIM2_NAND_TWHRE(0x1e))
 176 #define CONFIG_SYS_NAND_FTIM3           0x0
 177
 178 #define CONFIG_SYS_NAND_DDR_LAW         11
 179 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 180 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 181
 182 #if defined(CONFIG_MTD_RAW_NAND)
 183 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 184 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 185 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 186 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 187 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 188 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 189 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 190 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 191 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 193 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 194 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 195 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 196 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 197 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 198 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 199 #else
 200 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 201 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 202 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 203 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 204 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 205 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 206 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 207 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 208 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 209 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 210 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 211 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 212 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 213 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 214 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 215 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 216 #endif
 217
 218 #define CONFIG_HWCONFIG
 219
 220 /* define to use L1 as initial stack */
 221 #define CONFIG_L1_INIT_RAM
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 225 /* The assembler doesn't like typecast */
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 227                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 228                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 229 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 230 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 231 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 232
 233 /*
 234  * Serial Port
 235  */
 236 #define CONFIG_SYS_NS16550_SERIAL
 237 #define CONFIG_SYS_NS16550_REG_SIZE     1
 238 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 239 #define CONFIG_SYS_BAUDRATE_TABLE       \
 240         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 241 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 242 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 243 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 244 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 245
 246 /*
 247  * I2C
 248  */
 249
 250 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 251 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 252 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 253 #define I2C_MUX_CH_DEFAULT      0x8
 254
 255 #define I2C_MUX_CH_VOL_MONITOR  0xa
 256
 257 /* The lowest and highest voltage allowed for T208xRDB */
 258 #define VDD_MV_MIN                      819
 259 #define VDD_MV_MAX                      1212
 260
 261 /*
 262  * RapidIO
 263  */
 264 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 265 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 266 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 267 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 268 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 269 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 270 /*
 271  * for slave u-boot IMAGE instored in master memory space,
 272  * PHYS must be aligned based on the SIZE
 273  */
 274 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 275 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 276 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 277 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 278 /*
 279  * for slave UCODE and ENV instored in master memory space,
 280  * PHYS must be aligned based on the SIZE
 281  */
 282 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 283 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 284 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 285
 286 /* slave core release by master*/
 287 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 288 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 289
 290 /*
 291  * SRIO_PCIE_BOOT - SLAVE
 292  */
 293 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 294 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 295 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 296                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 297 #endif
 298
 299 /*
 300  * eSPI - Enhanced SPI
 301  */
 302
 303 /*
 304  * General PCI
 305  * Memory space is mapped 1-1, but I/O space must start from 0.
 306  */
 307 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 308 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 309 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 310 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 311 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 312
 313 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 314 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 315 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 316 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 317 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 318
 319 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 320 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 321 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 322 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 323 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 324
 325 /* controller 4, Base address 203000 */
 326 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 327 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 328 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 329
 330 /* Qman/Bman */
 331 #ifndef CONFIG_NOBQFMAN
 332 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 333 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 334 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 335 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 336 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 337 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 338 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 339 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 340 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 341                                         CONFIG_SYS_BMAN_CENA_SIZE)
 342 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 343 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 344 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 345 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 346 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 347 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 348 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 349 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 350 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 351 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 352 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 353                                         CONFIG_SYS_QMAN_CENA_SIZE)
 354 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 355 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 356
 357 #define CONFIG_SYS_DPAA_FMAN
 358 #define CONFIG_SYS_DPAA_PME
 359 #define CONFIG_SYS_PMAN
 360 #define CONFIG_SYS_DPAA_DCE
 361 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 362 #define CONFIG_SYS_INTERLAKEN
 363 #endif /* CONFIG_NOBQFMAN */
 364
 365 #ifdef CONFIG_SYS_DPAA_FMAN
 366 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 367 #define RGMII_PHY2_ADDR         0x02
 368 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 369 #define CORTINA_PHY_ADDR2       0x0d
 370 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 371 #define FM1_10GEC3_PHY_ADDR     0x00
 372 #define FM1_10GEC4_PHY_ADDR     0x01
 373 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 374 #define AQR113C_PHY_ADDR1       0x00
 375 #define AQR113C_PHY_ADDR2       0x08
 376 #endif
 377
 378 /*
 379  * USB
 380  */
 381
 382 /*
 383  * SDHC
 384  */
 385 #ifdef CONFIG_MMC
 386 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 387 #endif
 388
 389 /*
 390  * Dynamic MTD Partition support with mtdparts
 391  */
 392
 393 /*
 394  * Environment
 395  */
 396
 397 /*
 398  * Miscellaneous configurable options
 399  */
 400
 401 /*
 402  * For booting Linux, the board info and command line data
 403  * have to be in the first 64 MB of memory, since this is
 404  * the maximum mapped by the Linux kernel during initialization.
 405  */
 406 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 407
 408 /*
 409  * Environment Configuration
 410  */
 411 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 412 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 413
 414 #define __USB_PHY_TYPE          utmi
 415
 416 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 417         "hwconfig=fsl_ddr:"                                     \
 418         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 419         "bank_intlv=auto;"                                      \
 420         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 421         "netdev=eth0\0"                                         \
 422         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 423         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 424         "tftpflash=tftpboot $loadaddr $uboot && "               \
 425         "protect off $ubootaddr +$filesize && "                 \
 426         "erase $ubootaddr +$filesize && "                       \
 427         "cp.b $loadaddr $ubootaddr $filesize && "               \
 428         "protect on $ubootaddr +$filesize && "                  \
 429         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 430         "consoledev=ttyS0\0"                                    \
 431         "ramdiskaddr=2000000\0"                                 \
 432         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 433         "fdtaddr=1e00000\0"                                     \
 434         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 435         "bdev=sda3\0"
 436
 437 /*
 438  * For emulation this causes u-boot to jump to the start of the
 439  * proof point app code automatically
 440  */
 441 #define PROOF_POINTS                            \
 442         "setenv bootargs root=/dev/$bdev rw "           \
 443         "console=$consoledev,$baudrate $othbootargs;"   \
 444         "cpu 1 release 0x29000000 - - -;"               \
 445         "cpu 2 release 0x29000000 - - -;"               \
 446         "cpu 3 release 0x29000000 - - -;"               \
 447         "cpu 4 release 0x29000000 - - -;"               \
 448         "cpu 5 release 0x29000000 - - -;"               \
 449         "cpu 6 release 0x29000000 - - -;"               \
 450         "cpu 7 release 0x29000000 - - -;"               \
 451         "go 0x29000000"
 452
 453 #define HVBOOT                          \
 454         "setenv bootargs config-addr=0x60000000; "      \
 455         "bootm 0x01000000 - 0x00f00000"
 456
 457 #define ALU                             \
 458         "setenv bootargs root=/dev/$bdev rw "           \
 459         "console=$consoledev,$baudrate $othbootargs;"   \
 460         "cpu 1 release 0x01000000 - - -;"               \
 461         "cpu 2 release 0x01000000 - - -;"               \
 462         "cpu 3 release 0x01000000 - - -;"               \
 463         "cpu 4 release 0x01000000 - - -;"               \
 464         "cpu 5 release 0x01000000 - - -;"               \
 465         "cpu 6 release 0x01000000 - - -;"               \
 466         "cpu 7 release 0x01000000 - - -;"               \
 467         "go 0x01000000"
 468
 469 #include <asm/fsl_secure_boot.h>
 470
 471 #endif  /* __T2080RDB_H */